Sieu Mun Tang ce21a1a909 feat(intel): update Agilex5 DDR and IOSSM driver ... DDR and IOSSM driver code for Agilex5 platform, initialize the DDR/IOSSM in BL2 EL3 early flow. Change-Id: I3e4205171d9356190b60498cae322318520bb1c2 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>		2024-10-07 17:28:30 +02:00
..
aarch64	fix(intel): fix hardcoded mpu frequency ticks	2023-12-18 10:12:29 +08:00
drivers	fix(intel): update CCU configuration for Agilex5 platform	2024-09-25 21:45:17 +02:00
include	feat(intel): update Agilex5 DDR and IOSSM driver	2024-10-07 17:28:30 +02:00
lib/sha	feat(intel): enable VAB support for Intel products	2024-07-21 10:35:17 +08:00
sip	fix(intel): update memcpy to memcpy_s	2024-08-26 07:59:10 +08:00
soc	fix(intel): bridge ack timing issue causing fpga config hung	2024-09-23 17:21:46 +02:00
bl2_plat_mem_params_desc.c	feat(intel): enable SDMMC frontdoor load for ATF->Linux	2023-12-18 11:05:23 +08:00
socfpga_delay_timer.c	fix(intel): fix hardcoded mpu frequency ticks	2023-12-18 10:12:29 +08:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	fix(intel): update memcpy to memcpy_s	2024-08-26 07:59:10 +08:00
socfpga_ros.c	feat(intel): support query of fip offset using RSU	2024-01-16 13:26:21 +08:00
socfpga_sip_svc.c	fix(intel): add in missing ECC register	2024-08-23 13:41:25 +02:00
socfpga_sip_svc_v2.c	feat(intel): add intel_rsu_update() to sip_svc_v2	2023-06-13 15:44:26 +08:00
socfpga_storage.c	Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration	2024-01-19 11:08:14 +01:00
socfpga_topology.c	feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA	2023-07-05 09:08:34 +08:00
socfpga_vab.c	fix(intel): update memcpy to memcpy_s	2024-08-26 07:59:10 +08:00