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arm-trusted-firmware/plat/intel/soc/n5x/include
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Sieu Mun Tang b3d2850842 fix(intel): update Agilex5 BL2 init flow and other misc changes 
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
2024-10-09 20:04:16 +02:00
..
n5x_clock_manager.h fix(intel): update Agilex5 BL2 init flow and other misc changes 2024-10-09 20:04:16 +02:00
n5x_system_manager.h feat(intel): support QSPI ECC Linux for N5X 2023-12-22 00:39:55 +08:00
socfpga_plat_def.h fix(intel): update Agilex5 BL2 init flow and other misc changes 2024-10-09 20:04:16 +02:00