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arm-trusted-firmware/plat/intel/soc/n5x
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Sieu Mun Tang b3d2850842 fix(intel): update Agilex5 BL2 init flow and other misc changes 
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
2024-10-09 20:04:16 +02:00
..
include fix(intel): update Agilex5 BL2 init flow and other misc changes 2024-10-09 20:04:16 +02:00
soc fix(intel): revert back to use L4 clock 2023-12-22 11:39:50 +08:00
bl31_plat_setup.c fix(intel): bl31 overwrite OCRAM configuration 2023-11-03 23:45:15 +08:00
platform.mk feat(intel): enable SDMMC frontdoor load for ATF->Linux 2023-12-18 11:05:23 +08:00