Madhav Bhatt b3d25dca86 fix(xilinx): avoid unexpected variable update ... The commit 50ab13577f ("fix(xilinx): typecast expression to match data type") introduced a change where the isenabler1 variable is modified within the loop iterating over GICD_ISENABLER registers. Instead of computing the offset from the base address for each register, the offset is accumulated incorrectly, leading to an incorrect register read. As a result, some GIC enablers, including the RTC device were missed, so pm_set_wakeup_source was not called for them and the suspend-resume use case was failed because of that. Fix the logic to ensure the correct offset calculation for each iteration, preserving the intended behavior. Fixes: 50ab13577f fix(xilinx): typecast expression to match data type Change-Id: Iec5bafcbde21078545a37259b2cf0353585ef1fa Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com> Signed-off-by: Ronak Jain <ronak.jain@amd.com>		2025-03-06 20:20:41 -08:00
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common	fix(xilinx): avoid unexpected variable update	2025-03-06 20:20:41 -08:00
versal	refactor(xilinx): refactor console to support transfer list	2025-02-17 06:11:10 +00:00
versal_net	refactor(xilinx): refactor console to support transfer list	2025-02-17 06:11:10 +00:00
zynqmp	refactor(xilinx): refactor console to support transfer list	2025-02-17 06:11:10 +00:00