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fix(xilinx): typecast expression to match data type
This corrects the MISRA violation C2012-10.6: The value of a composite expression shall not be assigned to an object with wider essential type. Explicitly type casted to match the data type of composite expression. Change-Id: I0fd845496b4d6ac702027eb2075a23b15849f7d6 Signed-off-by: Nithin G <nithing@amd.com> Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
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parent
3951baa6a6
commit
50ab13577f
2 changed files with 27 additions and 12 deletions
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@ -111,9 +111,12 @@ int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
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*/
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void ipi_mb_open(uint32_t local, uint32_t remote)
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{
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mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
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uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
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uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
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mmio_write_32(idr_offset,
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IPI_BIT_MASK(remote));
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mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
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mmio_write_32(isr_offset,
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IPI_BIT_MASK(remote));
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}
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@ -125,7 +128,9 @@ void ipi_mb_open(uint32_t local, uint32_t remote)
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*/
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void ipi_mb_release(uint32_t local, uint32_t remote)
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{
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mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
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uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
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mmio_write_32(idr_offset,
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IPI_BIT_MASK(remote));
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}
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@ -142,12 +147,14 @@ int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
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{
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int ret = 0U;
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uint32_t status;
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uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
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uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
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status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
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status = mmio_read_32(obr_offset);
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if ((status & IPI_BIT_MASK(remote)) != 0U) {
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ret |= IPI_MB_STATUS_SEND_PENDING;
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}
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status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
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status = mmio_read_32(isr_offset);
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if ((status & IPI_BIT_MASK(remote)) != 0U) {
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ret |= IPI_MB_STATUS_RECV_PENDING;
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}
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@ -167,13 +174,14 @@ int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
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void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
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{
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uint32_t status;
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uint64_t trig_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_TRIG_OFFSET);
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uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
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mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
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mmio_write_32(trig_offset,
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IPI_BIT_MASK(remote));
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if (is_blocking != 0U) {
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do {
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status = mmio_read_32(IPI_REG_BASE(local) +
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IPI_OBR_OFFSET);
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status = mmio_read_32(obr_offset);
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} while ((status & IPI_BIT_MASK(remote)) != 0U);
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}
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}
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@ -188,7 +196,9 @@ void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
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*/
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void ipi_mb_ack(uint32_t local, uint32_t remote)
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{
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mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET,
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uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
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mmio_write_32(isr_offset,
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IPI_BIT_MASK(remote));
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}
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@ -202,7 +212,9 @@ void ipi_mb_ack(uint32_t local, uint32_t remote)
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*/
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void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
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{
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mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET,
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uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
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mmio_write_32(idr_offset,
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IPI_BIT_MASK(remote));
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}
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@ -216,6 +228,8 @@ void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
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*/
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void ipi_mb_enable_irq(uint32_t local, uint32_t remote)
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{
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mmio_write_32(IPI_REG_BASE(local) + IPI_IER_OFFSET,
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uint64_t ier_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IER_OFFSET);
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mmio_write_32(ier_offset,
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IPI_BIT_MASK(remote));
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}
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@ -56,7 +56,8 @@ void pm_client_set_wakeup_sources(uint32_t node_id)
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for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
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uint32_t base_irq = reg_num << ISENABLER_SHIFT;
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uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
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isenabler1 += (reg_num << 2);
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uint32_t reg = mmio_read_32((uint64_t)isenabler1);
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if (reg == 0U) {
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continue;
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