Jit Loon Lim 646a9a1615 fix(intel): update warm reset routine and bootscratch register usage ... Agilex5 platform: Boot scratch COLD6 register is meant for Customer use only. So, use Intel specific COLD3 register with [5:2]bits to determine the warm reset and SMP boot requests. Also handle the unaligned DEVICE/IO memory store and load in the assembly entrypoint startup code. Agilex, Stratix10, N5X platforms: Use only the LSB 4bits [3:0] of the boot scratch COLD6 register to detect the warm reset request. Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>		2025-01-13 16:31:42 +08:00
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include	fix(intel): update warm reset routine and bootscratch register usage	2025-01-13 16:31:42 +08:00
soc	fix(intel): revert back to use L4 clock	2023-12-22 11:39:50 +08:00
bl2_plat_setup.c	fix(intel): update outdated code for Linux direct boot	2024-10-16 23:36:49 +02:00
bl31_plat_setup.c	fix(intel): update preloaded_bl33_base for legacy product	2024-10-22 09:32:37 +08:00
platform.mk	Merge "feat(intel): add build option for boot source" into integration	2024-10-28 23:08:07 +01:00