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arm-trusted-firmware/include/lib/cpus
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Andrew Davis 81858a353f feat(ti): set L2 cache ECC and and parity on A72 cores 
The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c
2023-01-12 18:42:57 -06:00
..
aarch32 feat(ti): set L2 cache ECC and and parity on A72 cores 2023-01-12 18:42:57 -06:00
aarch64 feat(ti): set L2 cache ECC and and parity on A72 cores 2023-01-12 18:42:57 -06:00
errata_report.h Workaround for Cortex A78 erratum 1951500 2021-01-13 13:54:18 -06:00
wa_cve_2017_5715.h Fix MISRA defects in workaround and errata framework 2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h Fix MISRA defects in workaround and errata framework 2018-10-29 14:41:48 +00:00
wa_cve_2022_23960.h fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00