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feat(ti): set L2 cache ECC and and parity on A72 cores

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The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c
This commit is contained in:
Andrew Davis 2023-01-10 13:25:42 -06:00
parent aee2f33a67
commit 81858a353f
3 changed files with 9 additions and 0 deletions
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3
include/lib/cpus/aarch32/cortex_a72.h
View file

@ -43,6 +43,9 @@
******************************************************************************/
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)

3
include/lib/cpus/aarch64/cortex_a72.h
View file

@ -60,6 +60,9 @@
******************************************************************************/
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)

3
plat/ti/k3/common/k3_helpers.S
View file

@ -114,6 +114,9 @@ a72:
orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
#endif
/* Enable L2 ECC and parity with inline data */
orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
msr CORTEX_A72_L2CTLR_EL1, x0
isb
ret