Govindraj Raja 7455cd1721 fix(cpus): workaround for accessing ICH_VMCR_EL2 ... When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0) and then subsequently read in Non-secure state (SCR_EL3.NS==1), a wrong value might be returned. The same issue exists in the opposite way. Adding workaround in EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. For example, EL3 software should set SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for Non-secure(or Realm) state. EL3 software should clear SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for Secure state. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I9f0403601c6346276e925f02eab55908b009d957 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>		2025-02-03 10:14:09 -06:00
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aarch32	refactor(cpus): remove cpu specific errata funcs	2024-07-26 11:19:52 +01:00
aarch64	fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus	2025-01-30 16:45:35 -06:00
cpu-ops.mk	fix(security): enable WORKAROUND_CVE_2024_7881 build option	2025-01-30 16:45:35 -06:00
errata_common.c	fix(cpus): workaround for accessing ICH_VMCR_EL2	2025-02-03 10:14:09 -06:00
errata_report.c	refactor(cpus): directly invoke errata reporter	2024-07-26 11:19:52 +01:00