Boyan Karatotev ece8f7d734 refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only ... These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect EL2 (and lower) execution. Each feat_init_el3() is called long before any lower EL has had a chance to execute, so setting the bits at reset is redundant. Removing them from reset code also improves readability of the immutable EL3 state. Preserve the original intention for the TTA bit of "enabled for NS and disabled everywhere else" (inferred from commit messages d4582d3088 and 2031d6166a and the comment). This is because CPTR_EL3 will be contexted and so everyone will eventually get whatever NS has anyway. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3d24b45d3ea80882c8e450b2d9db9d5531facec1		2023-07-24 11:04:44 +01:00
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arch	refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only	2023-07-24 11:04:44 +01:00
bl1	style: remove useless trailing semicolon and line continuations	2023-03-09 14:59:08 +01:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	fix(tree): correct some typos	2023-05-09 15:57:12 +01:00
bl32	refactor(libc): clean up dependencies in libc	2022-09-22 13:23:49 +02:00
common	refactor(fdt-wrappers): fix for unit testing errors	2023-06-26 15:03:08 -05:00
drivers	Merge changes from topic "agilex5" into integration	2023-07-06 20:44:43 +02:00
dt-bindings	feat(dt-bindings): add TZC400 bindings for STM32MP13	2022-03-22 09:09:23 +01:00
export	fix: integer suffix macro definition	2023-06-20 15:22:19 +02:00
lib	refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only	2023-07-24 11:04:44 +01:00
plat	fix(fvp): adjust BL31 maximum size as per total SRAM size	2023-06-28 21:53:51 +01:00
services	chore: remove unused and undefined function	2023-06-06 08:19:06 -07:00
tools_share	feat(cert-create): add new option for CCA NV ctr	2023-05-25 16:40:43 -05:00