Grzegorz Jaszczyk 3c0024cc2c mvebu: cp110: fix spelling in register definition ... Use PF instead of PP post-fix, since it is referring to "Phase Final" (only G3 related register had correct spelling for relevant bit). Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>		2018-09-02 14:10:47 +03:00
..
arm	cci: Use dsb to wait before reading status register	2018-08-13 14:20:30 +01:00
auth	libc: Use printf and snprintf across codebase	2018-08-22 10:26:05 +01:00
cadence/uart	drivers: cadence: cdns: Update CDNS driver to support MULTI_CONSOLE_API	2018-01-19 15:21:12 -08:00
console	Console: Use callee-saved registers	2018-08-15 13:03:01 +01:00
coreboot/cbmem_console/aarch64	coreboot: Add support for CBMEM console	2018-01-19 15:21:12 -08:00
delay_timer	Fix MISRA rule 8.3 in common code	2018-02-28 17:18:21 +00:00
gpio	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
io	Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6	2018-07-19 17:11:32 +01:00
marvell	mvebu: cp110: fix spelling in register definition	2018-09-02 14:10:47 +03:00
mmc	drivers/mmc: Fix warning about usage of uninitialized variable	2018-08-10 14:58:08 +01:00
partition	libc: Use printf and snprintf across codebase	2018-08-22 10:26:05 +01:00
st	libc: Use printf and snprintf across codebase	2018-08-22 10:26:05 +01:00
synopsys	drivers/dw_mmc: migrate to mmc framework	2018-08-10 17:11:12 +08:00
ti/uart	drivers: ti: uart: Add TI specific 16550 initialization	2018-06-11 14:26:32 -05:00
ufs	drivers: fix switch statements to comply with MISRA rules	2018-03-26 12:43:05 +01:00