Jit Loon Lim 8a0a006af3 fix(altera): add in support for agilex5 b0 jtag id ... Support Agilex5 B0 jtag id for fpga reconfig. Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>		2025-02-10 12:22:06 +08:00
..
aarch64	fix(intel): update warm reset routine and bootscratch register usage	2025-01-13 16:31:42 +08:00
drivers	fix(intel): refactor SDMMC driver for Altera products	2024-10-25 09:38:51 +08:00
include	fix(altera): add in support for agilex5 b0 jtag id	2025-02-10 12:22:06 +08:00
lib/sha	feat(intel): enable VAB support for Intel products	2024-07-21 10:35:17 +08:00
sip	fix(intel): update memcpy to memcpy_s	2024-08-26 07:59:10 +08:00
soc	fix(altera): add in support for agilex5 b0 jtag id	2025-02-10 12:22:06 +08:00
bl2_plat_mem_params_desc.c	feat(intel): enable SDMMC frontdoor load for ATF->Linux	2023-12-18 11:05:23 +08:00
socfpga_delay_timer.c	fix(intel): update Agilex5 BL2 init flow and other misc changes	2024-10-09 20:04:16 +02:00
socfpga_image_load.c	fix(intel): update Agilex5 BL2 init flow and other misc changes	2024-10-09 20:04:16 +02:00
socfpga_psci.c	fix(intel): update warm reset routine and bootscratch register usage	2025-01-13 16:31:42 +08:00
socfpga_ros.c	feat(intel): support query of fip offset using RSU	2024-01-16 13:26:21 +08:00
socfpga_sip_svc.c	fix(altera): add in support for agilex5 b0 jtag id	2025-02-10 12:22:06 +08:00
socfpga_sip_svc_v2.c	feat(intel): add intel_rsu_update() to sip_svc_v2	2023-06-13 15:44:26 +08:00
socfpga_storage.c	fix(intel): refactor SDMMC driver for Altera products	2024-10-25 09:38:51 +08:00
socfpga_topology.c	feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA	2023-07-05 09:08:34 +08:00
socfpga_vab.c	fix(intel): update memcpy to memcpy_s	2024-08-26 07:59:10 +08:00