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https://github.com/ARM-software/arm-trusted-firmware.git
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4e772e6ba3
A Total Compute platform supports FVP and FPGA target. And it's possible that these two targets have different hardware components. For this reason, this patch introduces a new file tc-fpga.dtsi for FPGA related DT binding. As a result, this patch moves out FVP and FPGA specific macros into tc-fvp.dtsi and tc-fpga.dtsi respectively. Change-Id: I48d7d30d0c500cec5500f1a2a680e8b3a276ea99 Signed-off-by: Leo Yan <leo.yan@arm.com>
66 lines
1.3 KiB
Text
66 lines
1.3 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define BIG_CAPACITY 1024
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#define INT_MBOX_RX 300
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#define MHU_TX_ADDR 46040000 /* hex */
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#define MHU_RX_ADDR 46140000 /* hex */
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#if TARGET_FLAVOUR_FVP
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#define DPU_ADDR 4000000000
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#define DPU_IRQ 579
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#elif TARGET_FLAVOUR_FPGA
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#define DPU_ADDR 2cc00000
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#define DPU_IRQ 69
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#endif
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc-base.dtsi"
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/ {
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cpus {
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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};
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cpu-pmu {
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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};
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};
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