/*
 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>

#define LIT_CAPACITY			239
#define MID_CAPACITY			686
#define BIG_CAPACITY			1024

#define INT_MBOX_RX			300
#define MHU_TX_ADDR			46040000 /* hex */
#define MHU_RX_ADDR			46140000 /* hex */
#define MPAM_ADDR			0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ			3750000

#if TARGET_FLAVOUR_FVP
#define DPU_ADDR			4000000000
#define DPU_IRQ				579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR			2cc00000
#define DPU_IRQ				69
#endif

#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"

/ {
	cpus {
		CPU2:cpu@200 {
			clocks = <&scmi_dvfs 1>;
			capacity-dmips-mhz = <MID_CAPACITY>;
		};

		CPU3:cpu@300 {
			clocks = <&scmi_dvfs 1>;
			capacity-dmips-mhz = <MID_CAPACITY>;
		};

		CPU6:cpu@600 {
			clocks = <&scmi_dvfs 2>;
			capacity-dmips-mhz = <BIG_CAPACITY>;
		};

		CPU7:cpu@700 {
			clocks = <&scmi_dvfs 2>;
			capacity-dmips-mhz = <BIG_CAPACITY>;
		};
	};

	cpu-pmu {
		interrupt-affinity = <&CPU0>,  <&CPU1>,  <&CPU2>,  <&CPU3>,
				     <&CPU4>,  <&CPU5>,  <&CPU6>,  <&CPU7>;
	};
};