Juan Pablo Conde 14c27f8293 build(amu): restrict counters (RAZ) ... The use of AMU counters at the highest implemented exception level can expose information about them to lower exception levels, such as specific behavior happening in the CPU (e.g.: MPMM gear shifting in TC2). In order to prevent this, read accesses to AMU counters are restricted by default, so they are RAZ (read-as-zero) from lower exception levels from now on. Change-Id: I660b0928bea3fe09436ad53b0bb43c3067523178 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>		2024-05-10 13:39:15 -05:00
..
build-internals.rst	feat(arm): add trusty_sp_fw_config build option	2024-02-23 16:11:47 +00:00
build-options.rst	build(amu): restrict counters (RAZ)	2024-05-10 13:39:15 -05:00
docs-build.rst	docs: add instructions for PDF generation of docs	2023-08-10 10:42:14 +01:00
image-terminology.rst	docs(build): clarify getting started section	2022-11-16 14:06:48 +00:00
index.rst	docs(porting): move porting guide upper in table of contents	2023-04-11 10:11:04 +02:00
initial-build.rst	docs(build): clarify getting started section	2022-11-16 14:06:48 +00:00
prerequisites.rst	refactor(docs): restructure min requirements section	2024-04-24 08:20:22 +00:00
psci-lib-integration-guide.rst	docs: update PSCI reference	2023-06-15 09:46:43 +01:00
rt-svc-writers-guide.rst	feat(smccc): add vendor-specific el3 service	2024-05-06 09:42:11 -05:00
tools-build.rst	docs(build): clarify getting started section	2022-11-16 14:06:48 +00:00