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build(amu): restrict counters (RAZ)
The use of AMU counters at the highest implemented exception level can expose information about them to lower exception levels, such as specific behavior happening in the CPU (e.g.: MPMM gear shifting in TC2). In order to prevent this, read accesses to AMU counters are restricted by default, so they are RAZ (read-as-zero) from lower exception levels from now on. Change-Id: I660b0928bea3fe09436ad53b0bb43c3067523178 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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2 changed files with 4 additions and 3 deletions
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@ -23,8 +23,9 @@ Common build options
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is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
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- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
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zero at all but the highest implemented exception level. Reads from the
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memory mapped view are unaffected by this control.
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zero at all but the highest implemented exception level. External
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memory-mapped debug accesses are unaffected by this control.
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The default value is 1 for all platforms.
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- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
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``aarch64`` or ``aarch32`` as values. By default, it is defined to
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@ -280,7 +280,7 @@ endif
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ENABLE_FEAT_AMU ?= 0
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ENABLE_AMU_AUXILIARY_COUNTERS ?= 0
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ENABLE_AMU_FCONF ?= 0
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AMU_RESTRICT_COUNTERS ?= 0
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AMU_RESTRICT_COUNTERS ?= 1
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# Build option to enable MPAM for lower ELs.
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# Enabling it by default
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