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09c1edb84b
Cortex-X4 erratum 2957258 that applies to r0p0, r0p1 and is fixed in r0p2. In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize which register to return when reading the value of MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively. The workaround is to do an ISB prior to an MRS read to either MPIDR_EL1 and MIDR_EL1. SDEN documentation: https://developer.arm.com/documentation/109148/latest/ Change-Id: I2d8e7f4ce19ca2e1d87527c31e7778d81aff0279 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> |
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| .. | ||
| _static/css | ||
| about | ||
| components | ||
| design | ||
| design_documents | ||
| getting_started | ||
| perf | ||
| plat | ||
| process | ||
| resources | ||
| security_advisories | ||
| threat_model | ||
| tools | ||
| change-log.md | ||
| conf.py | ||
| global_substitutions.txt | ||
| glossary.rst | ||
| index.rst | ||
| license.rst | ||
| Makefile | ||
| porting-guide.rst | ||