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chore: rename Poseidon to Neoverse V3
Rename Neoverse Poseidon to Neoverse V3, make changes to related build flags, macros, file names etc. Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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Sona Mathew
parent
5f4acf98dd
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328d304d27
4 changed files with 101 additions and 101 deletions
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@ -87,7 +87,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
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+----------------------+
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| Neoverse-V2 |
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+----------------------+
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| Neoverse-Poseidon |
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| Neoverse-V3 |
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+----------------------+
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For all other cores impacted by Spectre-BHB, some of which that do not implement
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@ -4,25 +4,25 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_POSEIDON_H
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#define NEOVERSE_POSEIDON_H
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#ifndef NEOVERSE_V3_H
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#define NEOVERSE_V3_H
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#define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830)
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#define NEOVERSE_POSEIDON_V_MIDR U(0x410FD840)
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#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830)
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#define NEOVERSE_V3_MIDR U(0x410FD840)
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/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
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/* Neoverse V3 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* NEOVERSE_POSEIDON_H */
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#endif /* NEOVERSE_V3_H */
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@ -1,90 +0,0 @@
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/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_poseidon.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-poseidon generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_poseidon
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_poseidon, CVE(2022,23960)
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check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_poseidon_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
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NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc neoverse_poseidon_core_pwr_dwn
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cpu_reset_func_start neoverse_poseidon
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end neoverse_poseidon
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errata_report_shim neoverse_poseidon
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/* ---------------------------------------------
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* This function provides Neoverse-Poseidon specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_poseidon_regs, "aS"
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neoverse_poseidon_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_poseidon_cpu_reg_dump
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adr x6, neoverse_poseidon_regs
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mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
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ret
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endfunc neoverse_poseidon_cpu_reg_dump
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declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
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neoverse_poseidon_reset_func, \
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neoverse_poseidon_core_pwr_dwn
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declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_V_MIDR, \
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neoverse_poseidon_reset_func, \
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neoverse_poseidon_core_pwr_dwn
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90
lib/cpus/aarch64/neoverse_v3.S
Normal file
90
lib/cpus/aarch64/neoverse_v3.S
Normal file
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@ -0,0 +1,90 @@
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/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse V3 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v3
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v3, CVE(2022,23960)
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check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_v3_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
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NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc neoverse_v3_core_pwr_dwn
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cpu_reset_func_start neoverse_v3
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end neoverse_v3
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errata_report_shim neoverse_v3
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/* ---------------------------------------------
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* This function provides Neoverse V3 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v3_regs, "aS"
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neoverse_v3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v3_cpu_reg_dump
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adr x6, neoverse_v3_regs
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mrs x8, NEOVERSE_V3_CPUECTLR_EL1
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ret
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endfunc neoverse_v3_cpu_reg_dump
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declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
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neoverse_v3_reset_func, \
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neoverse_v3_core_pwr_dwn
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declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
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neoverse_v3_reset_func, \
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neoverse_v3_core_pwr_dwn
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