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8ae6b1ad6c
This patch implements SMCCC_ARCH_WORKAROUND_4 and allows discovery through SMCCC_ARCH_FEATURES. This mechanism is enabled if CVE_2024_7881 [1] is enabled by the platform. If CVE_2024_7881 mitigation is implemented, the discovery call returns 0, if not -1 (SMC_ARCH_CALL_NOT_SUPPORTED). For more information about SMCCC_ARCH_WORKAROUND_4 [2], please refer to the SMCCC Specification reference provided below. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 [2]: https://developer.arm.com/documentation/den0028/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I1b1ffaa1f806f07472fd79d5525f81764d99bc79
86 lines
2.7 KiB
ArmAsm
86 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x925.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x925, CVE(2024, 5660)
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check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1)
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workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x925, CVE(2024, 7881)
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check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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cpu_reset_func_start cortex_x925
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_x925
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x925_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_x925_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-X925 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x925_regs, "aS"
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cortex_x925_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x925_cpu_reg_dump
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adr x6, cortex_x925_regs
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mrs x8, CORTEX_X925_CPUECTLR_EL1
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ret
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endfunc cortex_x925_cpu_reg_dump
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declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
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cortex_x925_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_cortex_x925_7881, \
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cortex_x925_core_pwr_dwn
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