Exact

Exact Union RegExp

Boyan Karatotev c1b0a97b7a chore(cm): add MDCR_EL3.RLTE to context management ... The bit is already implicitly zero so no functional change. Adding it helps fully describe how we expect FEAT_TRF to behave. Change-Id: If7a7881e2b50188222ce46265b432d658a664c75 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>		2025-03-20 07:26:15 +00:00
..
amu	perf(amu): greatly simplify AMU context management	2025-02-25 08:50:46 +00:00
brbe	refactor(cm): change owning security state when a feature is disabled	2025-01-06 07:38:23 +00:00
debug	feat(debugv8p9): add support for FEAT_Debugv8p9	2024-07-18 13:49:43 -05:00
fgt	feat(fgt2): add support for FEAT_FGT2	2024-07-18 13:49:43 -05:00
fpmr	feat(fpmr): disable FPMR trap	2024-12-12 10:03:23 -06:00
mpam	refactor(cm): move MPAM3_EL3 reg to per world context	2023-12-21 12:37:21 +00:00
pauth	chore(pauth): remove redundant pauth_disable_el3() call	2023-04-28 08:09:14 +01:00
pmuv3	feat(pmuv3): setup per world MDCR_EL3	2025-01-24 10:09:08 +00:00
ras	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
sme	perf(cm): drop ZCR_EL3 saving and some ISBs and replace them with root context	2025-02-25 08:52:06 +00:00
spe	fix(cm): change back owning security state when a feature is disabled	2025-01-14 09:06:37 +00:00
sve	perf(cm): drop ZCR_EL3 saving and some ISBs and replace them with root context	2025-02-25 08:52:06 +00:00
sys_reg_trace	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
sysreg128	fix: add support for 128-bit sysregs to EL3 crash handler	2025-02-05 21:19:15 +01:00
tcr	feat(cm): handle asymmetry for FEAT_TCR2	2024-09-05 16:28:23 +01:00
trbe	fix(cm): change back owning security state when a feature is disabled	2025-01-14 09:06:37 +00:00
trf	chore(cm): add MDCR_EL3.RLTE to context management	2025-03-20 07:26:15 +00:00