chore(cm): add MDCR_EL3.RLTE to context management

The bit is already implicitly zero so no functional change. Adding it
helps fully describe how we expect FEAT_TRF to behave.

Change-Id: If7a7881e2b50188222ce46265b432d658a664c75
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev 2025-01-08 08:21:23 +00:00
parent c03884e51f
commit c1b0a97b7a
2 changed files with 7 additions and 2 deletions

View file

@ -697,6 +697,7 @@
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
#define MDCR_TPM_BIT (ULL(1) << 6)
#define MDCR_RLTE_BIT (ULL(1) << 0)
#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT
/* MDCR_EL2 definitions */

View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,8 +22,12 @@ void trf_enable(cpu_context_t *ctx)
* MDCR_EL3.TTRF = b0
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*
* MDCR_EL3.RLTE = b0
* Trace prohibited in Realm state, unless overridden by the
* IMPLEMENTATION DEFINED authentication interface.
*/
mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT | MDCR_RLTE_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}