Commit graph

12612 commits

Author SHA1 Message Date
Kathleen Capella
fd1479d919 fix(doc): match boot-order size to implementation
Docs had boot-order field as being u32 but code uses uint16_t.
FF-A specification does not specify a required size.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: Ia4c3fc66b9e733ea1417d34c2601bce1f81c4d32
2023-05-17 16:25:31 -04:00
Bipin Ravi
08d7a10157 Merge "docs(prerequisites): update software and libraries prerequisites" into integration 2023-05-16 22:22:08 +02:00
Govindraj Raja
0d7e702e4f docs(prerequisites): update software and libraries prerequisites
Update to use the following software:

- mbed TLS == 3.4.0
- (DTC) >= 1.4.7
- Ubuntu 22.04 for builds.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I384aab4dfee9cae9453eebf4091abe82ef9ccfaa
2023-05-16 17:36:18 +01:00
Manish Pandey
2834bc6b83 Merge "fix(tegra210): mark bits [23:17] as zero for Fast SMCs" into integration 2023-05-16 16:58:09 +02:00
Manish Pandey
20304ce22f Merge changes from topic "ja/mem_share_doc" into integration
* changes:
  docs(spm): threat model for memory sharing functionality
  docs(spm): add memory sharing documentation
2023-05-16 16:57:15 +02:00
Sandrine Bailleux
493d422363 Merge changes from topics "plat_tests_scalability", "sb/tc-plat-tests" into integration
* changes:
  test(tc): unify platform tests traces
  test(tc): return test failures count for tfm-testsuite
  test(tc): move platform tests in their own function
  test(tc): centralize platform error handling
  refactor(tc): define PLATFORM_TESTS for scale
2023-05-16 13:03:28 +02:00
Sandrine Bailleux
303ef33e7d test(tc): unify platform tests traces
Add some traces at the start and end of platform tests. These traces
are the same regardless of the set of platform tests we run (NV
counter tests / TF-M testsuite / future set of tests).

This makes it easier to integrate these tests in the CI because we can
now have a unified "expect" script for all platform tests, instead of
having one dedicated "expect" script for each possible set of tests.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5ec30a7a25d8a9a4a90e3338a9789acff7ad4843
2023-05-15 13:02:30 +02:00
Sandrine Bailleux
26207c2d33 test(tc): return test failures count for tfm-testsuite
When running the "tfm-testsuite" set of platform tests, we now count
the number of failed tests (in addition to printing a test summary)
and report that back to the caller,
i.e. tc_bl31_common_platform_setup().

This will be useful to consolidate the tests failure reporting code in
a subsequent patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I8e51f03869f3b2f264b6581b3bd2a53be0198057
2023-05-15 13:02:27 +02:00
Sandrine Bailleux
4eefbf1bf7 test(tc): move platform tests in their own function
This is a bit cleaner, as it avoids cluttering the normal boot execution
path. It also gives us the opportunity to mark the tests function with
the __dead2 attribute, which inform both the compiler and the developer
that the test function never returns (since it suspends booting).

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I082a34a840ef791a2ac4c1f59b19b32aeb0a9ec7
2023-05-15 13:02:24 +02:00
Sandrine Bailleux
57cc12c85c test(tc): centralize platform error handling
Note that this change only affects the platform tests execution
path. It has no impact on the normal boot flow.

Make individual test functions propagate an error code, instead of
calling the platform error handler at the point of failure. The latter
is now the responsibility of the caller - in this case
tc_bl31_common_platform_setup().

Note that right now, tc_bl31_common_platform_setup() does not look at
the said error code but this initial change opens up an opportunity to
centralize any error handling in tc_bl31_common_platform_setup(),
which we will seize in subsequent patches.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib282b64039e0b1ec6e6d29476fbaa2bcd33cb0c7
2023-05-15 13:02:19 +02:00
Kalyani Chidambaram Vaidyanathan
cb6c8efc4f fix(tegra210): mark bits [23:17] as zero for Fast SMCs
Per SMCCC documentation, bits [23:17] must be zero for Fast
SMCs. Other values are reserved for future use. Ensure that
these bits are zeroes for TEGRA_SIP_PMC_COMMANDS.

Commit f8a35797 introduced a check to return error if these
bits are not zero, thus breaking Tegra210 platforms. This
patch fixes the anomaly.

Change-Id: I19edc3b33c999a6fee6b86184233fba146316466
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2023-05-12 09:54:51 +01:00
J-Alves
ff8f1c5fe1 docs(spm): threat model for memory sharing functionality
Update the SPM threat model with information about FF-A v1.1
memory sharing functionality.

Change-Id: I65ea0d53aba8ac2f8432539968ceaab6be109ac8
Signed-off-by: J-Alves <joao.alves@arm.com>
2023-05-12 09:32:21 +01:00
J-Alves
cc63ff9762 docs(spm): add memory sharing documentation
Add documentation that explains implementation specific
relevant information from the update done to FF-A v1.1
memory sharing in Hafnium.

Change-Id: Ifc3c6b86c0545d53331207b017b990427ee84f2d
Signed-off-by: J-Alves <joao.alves@arm.com>
2023-05-12 09:32:21 +01:00
Manish Pandey
dcf430656c Merge "docs(psci): expound runtime instrumentation docs" into integration 2023-05-11 13:41:35 +02:00
Joanna Farley
3011e1afeb Merge changes from topic "ms/external_deps" into integration
* changes:
  feat(libc): add %c to printf/snprintf
  feat(compiler-rt): update source files
  chore(libfdt): update to v1.7.0 source files
2023-05-11 13:12:06 +02:00
Harrison Mutai
b1af2676f2 docs(psci): expound runtime instrumentation docs
Change-Id: I3c30b44d4196c30fd07373282150e543959fce1a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-05-11 12:11:43 +01:00
Maksims Svecovs
44d9706e54 feat(libc): add %c to printf/snprintf
Adds %c support for printf and snprintf to print one character. Required
by most recent MbedTLS 3.4.0.

Change-Id: I4d9b2725127a929d58946353324f99ff22b3b28b
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-05-11 10:32:28 +01:00
Maksims Svecovs
658ce7ad8e feat(compiler-rt): update source files
Update the compiler-rt source files to the tip of the llvm-project [1]
[1]: https://github.com/llvm/llvm-project/commit/d9683a7

Change-Id: Icec9ec73094a2b39b0240fc8253c36e7485d3a98
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-05-11 10:32:14 +01:00
Maksims Svecovs
058e017e51 chore(libfdt): update to v1.7.0 source files
Update libfdt to source files from v1.7.0 release.
Upstream commit:
039a99414e

Change-Id: I7e0475d2ddb819691f476e1753d1c899f8d7c278
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-05-11 10:28:47 +01:00
Manish Pandey
3331c33d03 Merge "feat(optee): add device tree for coreboot table" into integration 2023-05-11 11:14:50 +02:00
Manish Pandey
9d44b2b981 Merge "fix(n1sdp): add platform-specific power domain functions" into integration 2023-05-11 11:09:09 +02:00
Manish Pandey
5bfdb73270 Merge "fix(morello): add platform-specific power domain functions" into integration 2023-05-11 11:08:52 +02:00
Jeffrey Kardatzke
f4bbf43555 feat(optee): add device tree for coreboot table
This adds creation of a device tree that will be passed to OP-TEE.
Currently that device tree only contains the coreboot table per the
Linux coreboot device tree specification. This device tree is then
passed to OP-TEE so it can extract the CBMEM console information from
the coreboot table for logging purposes.

Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I6a26d335e16f7226018c56ad571cca77b81b0f6a
2023-05-11 10:46:57 +02:00
Manish Pandey
a63de43661 Merge "fix: increase BL32 limit" into integration 2023-05-11 10:46:36 +02:00
Manish V Badarkhe
c2a76122c8 fix: increase BL32 limit
BL32_LIMIT has been increased from 2MB to 4MB to accommodate
the latest tee.bin (it is around ~2.1MB).

Change-Id: I47b770bf23c23d38931a2b3316d076b829338d70
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Co-developed-by: Juan Pablo Conde <juanpablo.conde@arm.com>
2023-05-11 10:04:04 +02:00
Madhukar Pappireddy
e1eef33572 Merge "fix(spmd): fix build error with spmd" into integration 2023-05-11 00:44:49 +02:00
Govindraj Raja
fd51b21573 fix(spmd): fix build error with spmd
Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of
'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd'

So make 'plat_spmd_handle_group0_interrupt' dummy implementation
available just when spmd is enabled and SPMC_AT_EL3 is disabled.

Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-05-10 15:57:29 -05:00
Manish Pandey
8700c6f784 Merge "fix(psci): do not panic on illegal MPIDR" into integration 2023-05-10 18:56:46 +02:00
Manish V Badarkhe
b967ca06bd Merge "build(fpga): reduce cpu_libs to tc and neoverse" into integration 2023-05-10 18:34:31 +02:00
Daniel Boulby
3c3ea90c99 build(fpga): reduce cpu_libs to tc and neoverse
Change-Id: I20e88d5e712dafa7364b7932b8b4aaa9051bea55
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2023-05-10 15:43:29 +01:00
Joanna Farley
a18e975f00 Merge "docs: update release and code freeze dates" into integration 2023-05-10 15:16:40 +02:00
Manish Pandey
c84200ecd9 Merge "fix(pmu): unconditionally save PMCR_EL0" into integration 2023-05-10 14:12:25 +02:00
Manish V Badarkhe
41914de338 Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration
* changes:
  fix(msm8916): add timeout for crash console TX flush
  style(msm8916): use size macros
  feat(msm8916): expose more timer frames
  fix(msm8916): drop unneeded initialization of CNTACR
  build(msm8916): disable unneeded workarounds
  fix(msm8916): flush dcache after writing msm8916_entry_point
  fix(msm8916): print \r before \n on UART console
2023-05-09 23:29:52 +02:00
Manish Pandey
4bd8c929b4 Merge changes I1bfa797e,I0ec7a70e into integration
* changes:
  fix(tree): correct some typos
  fix(rockchip): use semicolon instead of comma
2023-05-09 22:05:52 +02:00
Manish Pandey
269f3daefb Merge changes from topic "mp/feat_ras" into integration
* changes:
  refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
  refactor(ras): replace RAS_EXTENSION with FEAT_RAS
2023-05-09 21:48:45 +02:00
Stephan Gerhold
7e002c8a13 fix(msm8916): add timeout for crash console TX flush
Resetting the UART DM controller while there are still remaining
characters in the FIFO often results in corruption on the UART receiver
side. To avoid this the msm8916 crash console implementation tries to
wait until the TX FIFO is empty.

Unfortunately this might spin forever if the transmitter was disabled
before it has fully finished transmitting. In this case the TXEMT bit
console_uartdm_core_flush is waiting for will never get set.

There seems to be no good way to detect if the transmitter is actually
enabled via the status registers. However, the TX FIFO is fairly small
and should not take too long to get flushed, so fix this by simply
limiting the amount of iterations with a short timeout.

Move the code to console_uartdm_core_init to ensure that this always
happens before resetting the transmitter (also during initialization).

Change-Id: I5bb43cb0b6c029bcd15e253d60d36c0b310e108b
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:46:27 +02:00
Stephan Gerhold
a27e3f7698 style(msm8916): use size macros
Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:46:18 +02:00
Stephan Gerhold
1781bf1c40 feat(msm8916): expose more timer frames
The memory-mapped generic timer on msm8916 has 7 timer frames, but
currently only one is exposed for usage in the non-secure world.

The platform port is currently only designed to be used as minimal PSCI
implementation, without secure world that could make use of the other
timer frames. Let's make all of them available to the normal world.

If needed this could still be changed later by reserving some timer
frames conditionally to a specific SPD being enabled in the build.

Change-Id: Ib59df16aa1fd3dbc875ab6369c133737830c98c6
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:44:58 +02:00
Stephan Gerhold
d833af3ab5 fix(msm8916): drop unneeded initialization of CNTACR
Normal world software is responsible to initialize CNTACR as needed.
There is no existing software for msm8916 that depends on having this
initialization in BL31 so drop it before anything starts to rely on it.

Related issue: https://github.com/ARM-software/tf-issues/issues/170

Change-Id: I9d037ab218c0c1c8a5d5523722013eba531f4728
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:44:51 +02:00
Stephan Gerhold
4a3e2cb355 build(msm8916): disable unneeded workarounds
The Cortex-A53 cores used in the msm8916 platform are not affected by
CVE-2017-5715 and CVE-2022-23960, so disable the workarounds for them
to drop the unused code from the compiled binary.

Change-Id: I9df5a4657c4fd90702b4db4e82d4ee1a2f60303c
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:44:44 +02:00
Stephan Gerhold
01ba69cd9b fix(msm8916): flush dcache after writing msm8916_entry_point
msm8916_entry_point is read with caches off (and even from two
different physical addresses when read through the "boot remapper"),
so it should be flushed to RAM after writing it.

Change-Id: I5c8193954bb28043b0a46fb2038f629bd8796c74
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:44:37 +02:00
Stephan Gerhold
3fb7e40a21 fix(msm8916): print \r before \n on UART console
UART drivers in TF-A are expected to print \r before \n. Some terminal
emulators expect \r\n as line endings by default so not doing this
causes broken line breaks.

Change-Id: I271a35a7c6907441bc71713b0b6a1da19da96878
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-05-09 21:44:29 +02:00
Madhukar Pappireddy
fdf9d768ea Merge changes from topic "srm/Errata_ABI_El3" into integration
* changes:
  docs(errata_abi): document the errata abi changes
  feat(fvp): enable errata management interface
  fix(cpus): workaround platforms non-arm interconnect
  refactor(errata_abi): factor in non-arm interconnect
  feat(errata_abi): errata management firmware interface
2023-05-09 21:15:54 +02:00
Bipin Ravi
dc53b9b385 Merge "fix(qemu-sbsa): enable FGT" into integration 2023-05-09 19:04:34 +02:00
Manish V Badarkhe
c214ced421 Merge changes from topic "bk/context_refactor" into integration
* changes:
  fix(gicv3): restore scr_el3 after changing it
  refactor(cm): make SVE and SME build dependencies logical
2023-05-09 18:15:01 +02:00
Madhukar Pappireddy
315f4f8a84 Merge "docs: update TZC secured DRAM map for FVP and Juno" into integration 2023-05-09 17:14:41 +02:00
Elyes Haouas
1b491eead5 fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
2023-05-09 15:57:12 +01:00
Elyes Haouas
8557d491b6 fix(rockchip): use semicolon instead of comma
Use semicolon insted of comma at the end of line.

Change-Id: I0ec7a70ec659333c98d586f7bebd5d91bd6c6cc1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09 15:57:00 +01:00
Manish Pandey
a26ecc1718 Merge changes I06b35f11,If80573d6 into integration
* changes:
  docs: remove plat_convert_pk() interface from release doc
  chore(io): remove io_dummy driver
2023-05-09 16:51:38 +02:00
Manish Pandey
236c0bf0c4 Merge "feat(mt8188): add MT8188 SPM debug logs" into integration 2023-05-09 16:00:50 +02:00