Commit graph

13987 commits

Author SHA1 Message Date
Sandrine Bailleux
fac4a843ca docs(contributing): various improvements
- Warn contributors that they need to register their email address in
   their Gerrit profile. Not doing so causes errors at patch submission
   and is a recurrent question on the mailing list.

 - Add some links where useful.

 - Remove confusing CGit link to TF-A source code. In the context of
   setting up a local copy of the repo for contributing patches,
   developers should rather clone it through Gerrit and this is best
   covered by the "Getting the TF-A Source" section of TF-A
   documentation.

 - Add references to the OpenCI documentation, which has a lot more
   details on some of the topics we briefly cover in the contribution
   guidelines.

 - Encourage the user to use the 'git review' command for patch
   submission, inline with OpenCI documentation instructions. This
   automatically sorts out which Gerrit server to push to and against
   which repo branch (thanks to the '.gitreview' configuration file in
   TF-A root directory).

 - Elaborate the Coverity Scan section.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I1131662d8bc3502967b269a599869ea130897efb
2024-01-29 15:24:01 +01:00
Manish V Badarkhe
6c74b55637 Merge "fix(mte): remove CTX_INCLUDE_MTE_REGS usage" into integration 2024-01-25 17:59:33 +01:00
Govindraj Raja
30788a8455 fix(mte): remove CTX_INCLUDE_MTE_REGS usage
commit@0a33adc058080433f73bde73895266068990245c
Deprecated CTX_INCLUDE_MTE_REGS but missed its usage in
context save and restore path.

Change-Id: I30544abdff2cf92ff05d2d4df46ffc6ff10611de
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-01-25 08:39:01 -06:00
Manish Pandey
19220a02c7 Merge "docs(cpufeat): clarify description of FEATURE_DETECTION macro" into integration 2024-01-25 11:15:15 +01:00
Andre Przywara
641571c728 docs(cpufeat): clarify description of FEATURE_DETECTION macro
The current documentation of the FEATURE_DETECTION build option seems
to suggest that this macro enables the dynamic runtime checking of
features, although this is done regardless of this debug feature.
FEATURE_DETECTION just adds the detect_arch_features() function to the
build and calls it early on, plus it enables the CPU errata order
checking.

Simplify the description of the FEATURE_DETECTION macro to make this
clear, and move the dynamic feature detection description into a
separate section, before all the specific ENABLE_FEAT_xxx explanations.

This also renames all mentioning of:
"... to align with the FEATURE_DETECTIION mechanism ..."
with:
"... to align with the ENABLE_FEAT mechanism ..."
in the description of each feature.

Change-Id: I5f4dd2d1e43bd440687b7cee551d02ec853d4e23
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-01-24 20:51:09 +00:00
Lauren Wehrmeister
07da4854e9 Merge changes from topics "rcar-tools-fix", "toolchain-cleanup" into integration
* changes:
  build: remove the `NM` variable
  build: prefer `gcc-ar` over `ar`
  build: add `--no-warn-rwx-segments` when linking with GCC
  build: always use the C compiler to assemble
  build: always use the C compiler to preprocess
  fix(rcar): fix implicit rule invocations in tools
2024-01-24 16:11:22 +01:00
Manish V Badarkhe
61dfdfd4db Merge "refactor(mte): deprecate CTX_INCLUDE_MTE_REGS" into integration 2024-01-24 11:05:32 +01:00
Sandrine Bailleux
fc26a0fcac Merge "feat(qemu-sbsa): handle memory information" into integration 2024-01-24 07:57:49 +01:00
Lauren Wehrmeister
3f02459572 Merge changes from topic "errata" into integration
* changes:
  fix(cpus): workaround for Cortex-A78C erratum 2683027
  fix(cpus): workaround for Cortex-X3 erratum 2266875
  fix(cpus): workaround for Cortex-X3 erratum 2302506
2024-01-23 21:43:06 +01:00
Govindraj Raja
0a33adc058 refactor(mte): deprecate CTX_INCLUDE_MTE_REGS
Currently CTX_INCLUDE_MTE_REGS is used for dual purpose,
to enable allocation tags register and to context save and restore
them and also to check if mte feature is available.

To make it more meaningful, remove CTX_INCLUDE_MTE_REGS
and introduce FEAT_MTE. This would enable allocation tags register
when FEAT_MTE is enabled and also supported from platform.

Also arch features can be conditionally enabled disabled based on
arch version from `make_helpers/arch_features.mk`

Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-01-23 11:58:55 -06:00
Sandrine Bailleux
d4a770a99b Merge "fix(intel): update nand driver to match GHRD design" into integration 2024-01-23 16:03:26 +01:00
Sandrine Bailleux
4b8e507822 Merge changes Ib481fade,Id4070b46,I4ac997cd into integration
* changes:
  feat(rcar3): update IPL and Secure Monitor Rev.4.0.0
  feat(rcar3): add cache operations to boot process
  feat(rcar3): change MMU configurations
2024-01-23 15:20:21 +01:00
Manish Pandey
e6a0994c02 Merge changes from topic "st-bsec-otp" into integration
* changes:
  feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
  feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
  fix(stm32mp2): add missing include
  feat(st): do not directly call BSEC functions in common code
  feat(st): use stm32_get_otp_value_from_idx() in BL31
  refactor(st): update test for closed chip
  refactor(st-bsec): improve BSEC driver
  refactor(st): use dashes for BSEC node names
2024-01-23 12:54:09 +01:00
Olivier Deprez
9f9b4814c5 Merge "fix(marvell-tools): include mbedtls/version.h before use" into integration 2024-01-23 10:55:11 +01:00
Girisha Dengi
a773f4121b fix(intel): update nand driver to match GHRD design
Update nand driver to match GHRD design, fix row
address calculation method and other misc updates.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1cb3dda43e767ba243fbe89bfa18818db321c5c2
2024-01-23 00:05:11 +08:00
Joanna Farley
1064bc6c8c Merge changes from topic "idling-during-subsystem-restart" into integration
* changes:
  fix(xilinx): add console_flush() before shutdown
  fix(xilinx): fix sending sgi to linux
  feat(xilinx): add new state to identify cpu power down
  feat(xilinx): request cpu power down from reset
  feat(xilinx): power down all cores on receiving cpu pwrdwn req
  feat(xilinx): add handler for power down req sgi irq
  feat(xilinx): add wrapper to handle cpu power down req
  fix(versal-net): use arm common GIC handlers
  fix(xilinx): rename macros to align with ARM
2024-01-22 16:12:02 +01:00
Joanna Farley
b7e85c7cee Merge "feat(versal): extend platform address space sizes" into integration 2024-01-22 16:07:46 +01:00
Joanna Farley
c0bf07e077 Merge "fix(xilinx): deprecate SiP service count query" into integration 2024-01-22 16:07:03 +01:00
Manish V Badarkhe
99f9aacd20 Merge "docs(threat-model): supply chain threat model TF-A" into integration 2024-01-22 14:45:17 +01:00
Sandrine Bailleux
2109aadd97 Merge "feat(rcar3): enable the stack protection" into integration 2024-01-22 14:31:45 +01:00
Olivier Deprez
81704f5d30 Merge "docs(security): security advisory for CVE-2023-49100" into integration 2024-01-22 10:41:55 +01:00
Xiong Yining
8b7dd8397d feat(qemu-sbsa): handle memory information
As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory address

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: Ib7bce3a65c817a5b3bef6c9e0a459c7ce76c7e35
2024-01-22 02:54:47 +00:00
Hieu Nguyen
516a98ef27 feat(rcar3): update IPL and Secure Monitor Rev.4.0.0
Update the version to match release versioning scheme.
No functional change.

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Change-Id: Ib481fade925f74dbea1dd2b39c1abfab888379e4
2024-01-21 15:36:30 +01:00
Toshiyuki Ogasahara
7e06b06753 feat(rcar3): add cache operations to boot process
Add cache operations because BL2 disabled MMU at the end of the boot
process, but did not clean/invalidate for the cache used by MMU.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Id4070b46103ca2b50788b3a99f6961a35df24418
2024-01-21 15:36:30 +01:00
Toshiyuki Ogasahara
5e8c2d8e23 feat(rcar3): change MMU configurations
Always enable MMU and control access protection.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I4ac997cda2985746b2bf97ab9e4e5ace600f43ca
2024-01-21 15:36:30 +01:00
Toshiyuki Ogasahara
cfa466ab73 feat(rcar3): enable the stack protection
This commit changes ENABLE_STACK_PROTECTOR value to "strong" for
enabling the stack protector by canary.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ice351d23c98daf12737a5e65cef743035d62dabe
2024-01-21 15:36:29 +01:00
laurenw-arm
b908814c74 docs(threat-model): supply chain threat model TF-A
Software supply chain attacks aim to inject malicious code into a
software product. There are several ways a malicious code can be
injected into a software product (open-source project).

These include:
- Malicious code commits
- Malicious dependencies
- Malicious toolchains

This document provides analysis of software supply chain attack
threats for the TF-A project

Change-Id: I03545d65a38dc372f3868a16c725b7378640a771
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-19 14:50:24 -06:00
Lauren Wehrmeister
57410eebe6 Merge "docs(threat-model): add threat model for PSA FWU and TBBR FWU(recovery)" into integration 2024-01-19 21:39:59 +01:00
Madhukar Pappireddy
0ec25e386a Merge "fix(spm): silence warning in sp_mk_generator" into integration 2024-01-19 17:33:05 +01:00
Madhukar Pappireddy
5abc58be59 Merge changes from topic "kc/dir_msg_req2" into integration
* changes:
  feat(spmd): add FFA_MSG_SEND_DIR_RESP2
  feat(spmd): add FFA_MSG_SEND_DIR_REQ2
2024-01-19 16:22:19 +01:00
Manish Pandey
48461ec939 Merge "style(hooks): copyright year check as per author email" into integration 2024-01-19 14:29:52 +01:00
Akshay Belsare
93d1f4bc74 style(hooks): copyright year check as per author email
Add a check in pre-commit hook to check the
- copyright header is present for the authors organisation.
- the copyright year for the copyright header is updated.

The author email id is parsed to get the organization. Depending upon
the parsed info, the copyright header for the organization is checked
if its present in the file(s) or not.
If the copyright header is present in the file(s) then the copyright
year is checked.

If the copyright header is not present or the copyright year in the
header is not updated it is highlighted to the author
which the user then needs to incorporate in the change accordingly.

To enable this check, the case statement in
.husky/pre-commit.copyright needs to be modified to add the domain
from the email id and corresponding copyright header of the
organisation.

Change-Id: I4dedb68248b3dae997d887dd380155fe326d071d
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
2024-01-19 14:29:29 +01:00
Manish V Badarkhe
3d43bf5580 Merge changes from topic "cca_dtb" into integration
* changes:
  feat(arm): add COT_DESC_IN_DTB option for CCA CoT
  feat(fvp): add CCA CoT in DTB support
  docs(arm): update TBBR CoT dtsi file name in doc
  feat(dt-bindings): introduce CCA CoT, rename TBBR
2024-01-19 11:40:02 +01:00
Manish V Badarkhe
bb4d7d7195 docs(threat-model): add threat model for PSA FWU and TBBR FWU(recovery)
Added a threat model for PSA firmware update as well as TBBR FWU aka
firmware recovery.

Change-Id: I2396e13144076d7294f61f6817e1a8646225c6c2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2024-01-19 10:23:36 +00:00
Sandrine Bailleux
51ff56e447 Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration 2024-01-19 11:08:14 +01:00
Sandrine Bailleux
b3a7396d0e Merge changes Iaa189c54,I8856b495 into integration
* changes:
  feat(intel): enable query of fip offset on RSU
  feat(intel): support query of fip offset using RSU
2024-01-19 10:44:29 +01:00
Sandrine Bailleux
781f9c52a6 Merge changes from topic "cca_dtb" into integration
* changes:
  docs(fconf): update bindings for multi-RoT CoTs
  feat(fconf): support signing-key in root cert node
2024-01-19 10:07:49 +01:00
laurenw-arm
b76a43c938 feat(arm): add COT_DESC_IN_DTB option for CCA CoT
Add support for BL2 to get the CCA chain of trust description
through the Firmware Configuration Framework (FCONF). This makes
it possible to export the part of the CCA chain of trust enforced
by BL2 in BL2's configuration file (TB_FW_CONFIG DTB file). BL2
will parse it when setting up the platform.

This feature can be enabled through the COT_DESC_IN_DTB=1 option.
The default behaviour (COT_DESC_IN_DTB=0) remains to hard-code
the CCA CoT into BL2 image.

Change-Id: Iec4f623d5e42b7c166beeb3ad6b35d918969f7e2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-18 13:55:07 -06:00
laurenw-arm
4c79b86ed6 feat(fvp): add CCA CoT in DTB support
Adding support for CCA CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file
in DTB format. With this, the CoT description may be updated without
rebuilding BL2 image. This feature can be enabled by building BL2
with COT_DESC_IN_DTB=1 and COT=cca. The default behaviour remains to
embed the CoT description into BL2 image.

Change-Id: I5912aad5ae529281a93a76e6b8f4b89d867445fe
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-18 13:55:07 -06:00
laurenw-arm
dc35bd320c docs(arm): update TBBR CoT dtsi file name in doc
Change-Id: I31ebee7574f5133aadbf2767377fd74a21775ce5
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-18 13:55:07 -06:00
laurenw-arm
c4b35cebff feat(dt-bindings): introduce CCA CoT, rename TBBR
Add CCA CoT DTB and rename generic CoT DTB to TBBR CoT DTB

This allows CCA platforms to get their chain of trust description
from a configuration file, rather than hard-coding it into the
firmware itself.

Change-Id: I114788a5d21b9a8d625239cfb71b442d204e3654
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-18 13:54:57 -06:00
laurenw-arm
0de9a12c89 docs(fconf): update bindings for multi-RoT CoTs
Update CoT binding documentation to add the signing-key property
as optional in root-certificates and add rot_keys node

Change-Id: I1d1fbc0394275520cfa43213d5b7006e51990fdd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-18 13:53:27 -06:00
Kathleen Capella
0651b7beb7 feat(spmd): add FFA_MSG_SEND_DIR_RESP2
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_RESP2 interface.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: Ibd0546ecd71d004804e6e18b27a4728a21259fa0
2024-01-18 14:44:50 -05:00
Kathleen Capella
cc6047b3de feat(spmd): add FFA_MSG_SEND_DIR_REQ2
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_REQ2 interface.
Handler validates security states of sender/receiver pairs
and forwards the call to other world if necessary.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I02a60362d8d9a50fcc0b6a84753cba274ba5eb1b
2024-01-18 14:44:50 -05:00
laurenw-arm
04ac0b3c27 feat(fconf): support signing-key in root cert node
Until now we have only supported describing chain of trusts through the
CoT DTB with a single ROTPK so the signing key for root certificates was
implicit. Therefore signing key was not a supported property in the
root certificates node.

Now we want to extend that to describe CoTs with mulitiple roots of
trust so we need a way to specify for each root certificate with which
ROTPK it should be verified. For that, we reuse the 'signing-key'
property already in use for the non-root certificates, but we make it
optional for root certificates in single-RoT CoTs and for root
certificates signed with the default ROTPK in multi-RoT CoTs.

Change-Id: I41eb6579e8f1d01eaf10480fe5e224d2eed9c736
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2024-01-18 13:18:09 -06:00
Manish V Badarkhe
9653570e28 Merge "feat(memmap): add RELA section display" into integration 2024-01-18 19:19:56 +01:00
Manish Pandey
d1eb4e2377 docs(security): security advisory for CVE-2023-49100
Reported-by: Christian Lindenmeier <christian.lindenmeier@fau.de>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I13fa93a65e5017dae6c837e88cd80bda72d4c2a3
2024-01-18 17:40:26 +00:00
Bipin Ravi
a5ea5aa441 Merge "docs(threat-model): provide PSR specification reference" into integration 2024-01-18 17:31:00 +01:00
Chris Kay
1685b42065 build: remove the NM variable
No part of the build system uses the `NM` variable, which is usually
used to dump symbol tables from compiled images. This change removes all
declarations of it.

Change-Id: I796ff365e6a7f97d21678f1c8cf8b59bfbb1ae9c
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-01-18 13:58:04 +00:00
Chris Kay
7e38758925 build: prefer gcc-ar over ar
The `gcc-ar` wrapper exists to make it easier to support LTO on some
versions of GCC. The two commands are compatible, accepting exactly the
same arguments, so this change moves us to `gcc-ar` to ensure that we
are configuring LTO correctly.

Change-Id: I24a4cfaad29d35b09f847299081f83ca9b41aa8a
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-01-18 13:58:03 +00:00