5 commits

Author	SHA1	Message	Date
Mahesh Rao	6cbe2c5d19	feat(intel): enable query of fip offset on RSU ... Enable query of fip offset from QSPI on RSU boot for Intel agilex and intel agilex5 platform Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1 Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>	2024-01-16 13:26:35 +08:00
Sieu Mun Tang	b727664e0d	fix(intel): add HPS remapper to remap base address for SDM ... Remap base address for SDM to access DRAM. Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>	2023-12-22 00:26:42 +08:00
Sieu Mun Tang	68820f6421	fix(intel): temporarily workaround for Zephyr SMP ... Temporarily workaround for Zephyr SMP testing. Change-Id: I9d2d209e9f384d079f0311b3a8b0b760e0566877 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>	2023-11-03 21:16:24 +08:00
Sieu Mun Tang	1af7bf71c0	fix(intel): resolved coverity checking ... Coverity checking fix. Resolved unused value, deadcode and uninit. 1. CID: 395326 2. CID: 395327 3. CID: 395328 4. CID: 395329 5. CID: 395330 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I86b8af28dc345542b142ce53e1935bb855888238	2023-07-11 00:06:19 +08:00
Jit Loon Lim	7931d3322d	feat(intel): platform enablement for Agilex5 SoC FPGA ... This patch is used to enable platform enablement for Agilex5 SoC FPGA. New feature: 1. Added ATF->Zephyr boot option 2. Added xlat_v2 for MMU 3. Added ATF->Linux boot option 4. Added SMP support 5. Added HPS bridges support 6. Added EMULATOR support 7. Added DDR support 8. Added GICv3 Redistirbution init 9. Added SDMMC/NAND/Combo Phy support 10. Updated GIC as secure access 11. Added CCU driver support 12. Updated product name -> Agilex5 13. Updated register address based on y22ww52.2 RTL 14. Updated system counter freq to 400MHz Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009	2023-07-05 10:11:22 +08:00