Commit graph

12489 commits

Author SHA1 Message Date
Nicola Mazzucato
b2836dfef6 docs: fix rendering for code blocks in SPM
Two sample build command code blocks are not correctly
rendered by the documentation generator.

Fix that by adding newlines.

Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: I1bb075ea4fc8e3230307548e40daecf2a79bae8d
2023-05-01 10:22:05 +01:00
Manish Pandey
48a65ec31a Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integration 2023-04-28 18:03:37 +02:00
Manish Pandey
76b225d41d Merge "docs(juno): refer to SCP v2.12.0" into integration 2023-04-28 15:58:05 +02:00
Manish Pandey
fe38cc6897 feat(fvp): introduce PLATFORM_TEST_EA_FFH config
FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the scenarios sensibly we need a proper handling when the FVP is
under test so that we do not change the default behavior.

Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI
scripts and implement a proper handling for Sync EA and SErrors from
lower EL.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b
2023-04-28 12:50:28 +01:00
Manish V Badarkhe
e31de867a2 Merge "fix(ras): do not put RAS check before esb macro" into integration 2023-04-28 12:08:37 +02:00
Manish V Badarkhe
a49bb6f838 Merge "docs: fix a typo in the glossary" into integration 2023-04-28 12:08:09 +02:00
Manish Pandey
1ff41ba333 Merge "feat(sme): enable SME2 functionality for NS world" into integration 2023-04-28 11:57:25 +02:00
Joanna Farley
7f95003bdb Merge "build(fvp): reduce the number of cpu libraries included by default" into integration 2023-04-28 00:16:11 +02:00
Joanna Farley
b39af24fb7 Merge "style(xilinx): fix AMD copyright format" into integration 2023-04-28 00:13:03 +02:00
Jayanth Dodderi Chidanand
03d3c0d729 feat(sme): enable SME2 functionality for NS world
FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.

This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.

Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.

Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2023-04-27 16:02:27 +01:00
Manish Pandey
7d5036b8ec fix(ras): do not put RAS check before esb macro
Macro esb used in TF-A executes the instruction "esb" and is kept under
RAS_EXTENSION macro. RAS_EXTENSION, as it stands today, is only enabled
for platforms which wants RAS errors to be handled in Firmware while esb
instruction is available when RAS architecture feature is present
irrespective of its handling.
Currently TF-A does not have mechanism to detect whether RAS is present
or not in HW, define this macro unconditionally.

Its harmless for non-RAS cores as this instruction executes as NOP.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I556f2bcf5669c378bda05909525a0a4f96c7b336
2023-04-27 12:59:39 +01:00
Sandrine Bailleux
6fc9c1cdb9 docs: fix a typo in the glossary
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I4c76fde5e487ab4b2495f1ea692ae07f8be81d57
2023-04-27 13:29:56 +02:00
Madhukar Pappireddy
69d643c5f4 Merge "fix(ufs): poll UCRDY for all commands" into integration 2023-04-27 00:36:55 +02:00
Madhukar Pappireddy
2499e66929 Merge changes from topic "ti-sci-cleanup" into integration
* changes:
  feat(ti): synchronize access to secure proxy threads
  refactor(ti): remove inline directive from ti_sci and sec_proxy drivers
  refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response
  feat(ti): add sub and patch version number support
2023-04-26 20:36:31 +02:00
Joanna Farley
1982a6ac62 Merge "docs: patch Poetry build instructions" into integration 2023-04-26 16:45:02 +02:00
Boyan Karatotev
0dcb03b6b1 build(fvp): reduce the number of cpu libraries included by default
The fvp build includes a very large number of cpus so that it can run on
a wide range of models. One config (HW_ASSISTED_COHERENCY=1
CTX_INCLUDE_AARCH32_REGS=0) includes an unusually large number of cpus.
Well, the list is quite arbitrary and incomplete. As we're currently out
of BL31 space on the fvp, remove all that are not routinely run in the
CI to buy us some time.

Also use the opportunity to reorder the list into something searchable.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8c6cad41327451edf0d3a0e92c43d6c72c254aac
2023-04-26 15:12:26 +01:00
Sandrine Bailleux
00cdd81ea7 Merge changes from topics "sb/deprecate-cryptocell", "sb/deprecation-policy" into integration
* changes:
  docs: deprecate CryptoCell-712/713 drivers
  docs: split deprecated interfaces and drivers
  docs: extend deprecation policy
2023-04-26 13:39:28 +02:00
Joanna Farley
89bc91a1ad Merge changes from topic "align-sections" into integration
* changes:
  build(trp): sort sections by alignment by default
  build(tsp): sort sections by alignment by default
  build(sp-min): sort sections by alignment by default
  build(bl31): sort sections by alignment by default
  build(bl2u): sort sections by alignment by default
  build(bl2): sort sections by alignment by default
2023-04-26 13:20:23 +02:00
Chris Kay
7cff6565bc docs(juno): refer to SCP v2.12.0
Change-Id: I2844fb569abcc403525982162484dc0aa7e5a9d6
Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-04-26 12:07:50 +01:00
Manish Pandey
44fcbb4a12 Merge "docs(juno): update SCP downloads link" into integration 2023-04-26 12:59:41 +02:00
Manish Pandey
1d1d93f129 Merge "build(bl1): sort sections by alignment by default" into integration 2023-04-26 12:56:57 +02:00
Madhukar Pappireddy
d5f19c49ba Merge "fix: add missing click dependency" into integration 2023-04-25 18:30:29 +02:00
Rohit Ner
6e57b2f00e fix(ufs): poll UCRDY for all commands
Host must only set UICCMD if HCS.UCRDY is set to 1.
At present, SW polls for UCRDY only before sending DME_GET.
Generalise this behaviour for DME_SET, DME_LINKSTARTUP,
DME_HIBERNATE_EXIT by moving polling logic inside ufshc_send_uic_cmd.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: Iece777f803a660fdd144a073834c221e889371a6
2023-04-25 09:29:54 -07:00
Manish Pandey
0df3824b73 Merge "refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED" into integration 2023-04-25 18:09:29 +02:00
Harrison Mutai
95f4abed84 docs: patch Poetry build instructions
Some parts of the documentation referring to Poetry provides incorrect
build instructions and has some minor formatting errors. Reformat the
bits that require formatting, and fix the build instructions. These
were originally part of the patch stack that added Poetry support but
were accidentally reverted prior to merge.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I336d3a7bbe99f75262430ae436f8ebc2cb050d2c
2023-04-25 16:18:10 +01:00
Andre Przywara
88727fc3ec refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED
At the moment we only support FEAT_DIT to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_DIT=2), by splitting
is_armv8_4_dit_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed).

We use ENABLE_DIT in two occassions in assembly code, where we just set
the DIT bit in the DIT system register.
Protect those two cases by reading the CPU ID register when ENABLE_DIT
is set to 2.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-25 15:09:30 +01:00
Manish V Badarkhe
33b4041d98 Merge "refactor(morello): remove duplication of platform information struct" into integration 2023-04-25 14:27:26 +02:00
Manish Pandey
e7f56d8331 Merge "feat(tcr2): add FEAT_TCR2 to the changelog" into integration 2023-04-25 14:04:22 +02:00
Manish Pandey
50e609f47c Merge "fix(cpus): do not put RAS check before using esb" into integration 2023-04-25 10:18:34 +02:00
Sandrine Bailleux
100f56d873 Merge "docs(threat-model): add a notes related to the Measured Boot" into integration 2023-04-25 08:58:50 +02:00
Bipin Ravi
760fbfc490 Merge "feat(gcs): support guarded control stack" into integration 2023-04-25 07:50:22 +02:00
Bipin Ravi
833cbe577e Merge "docs(maintainers): make Jimmy Brisson a code owner" into integration 2023-04-24 21:49:39 +02:00
Harrison Mutai
ff12683e87 fix: add missing click dependency
Click is used in parts of the CI scripts (see run_config/fvp-linux.tc
for instance), add it back as part of a new dependency group. Future
dependencies that are required only in CI should be added to the
``ci`` dependency group.

Change-Id: I5da7fea703495dd4006d86334626f126a850bb10
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-04-24 17:37:38 +01:00
Manish Pandey
9ec2ca2d45 fix(cpus): do not put RAS check before using esb
If RAS Extension is not implemented esb instruction executes as a NOP.
No need to have a check for RAS presence in the code.
Also, The handler is related to a synchronous exceptions which
implicitly is part of BL31 image only, so remove that check too.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If4264504cba9f0642b7b9c581ae66cd4deace32b
2023-04-24 17:32:22 +01:00
Manish Pandey
93e3b32273 Merge "fix(fvp): correct ehf priority for SPM_MM" into integration 2023-04-24 17:54:40 +02:00
Manish Pandey
fb2fd558d8 fix(fvp): correct ehf priority for SPM_MM
PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS
priority. Which is not allowed by exception handling framework and
causes build failure if both SPM_MM and RAS is enabled.

To fix this problem assign SP a different priority than RAS.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iff64ac547f0966c0d94ac7c3ab0eb1e3151fb314
2023-04-24 17:49:00 +02:00
Sandrine Bailleux
7c7e7b621a Merge changes from topic "mb/trusted-boot-update" into integration
* changes:
  refactor(auth)!: unify REGISTER_CRYPTO_LIB
  refactor(auth): replace plat_convert_pk
  docs(auth): add auth_decrypt in CM chapter
  feat(auth): compare platform and certificate ROTPK for authentication
  docs(auth): add 'calc_hash' function's details in CM
2023-04-24 15:46:26 +02:00
Sandrine Bailleux
ac57cf2fb6 Merge "docs: add a note about downstream platforms" into integration 2023-04-24 15:11:36 +02:00
Sandrine Bailleux
47c8dcfde7 docs: deprecate CryptoCell-712/713 drivers
We plan to deprecate the CryptoCell-712 and CryptoCell-713 drivers in
TF-A release v2.9 and eventually remove the code from the tree in
release 3.0.

The only upstream platforms which use these drivers today are the Arm
Ltd developpment platforms, such as Juno.

Write this information down into the "Release Processes" document.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib064292733a271ecbff0dde315911017e2c4da7e
2023-04-24 15:09:31 +02:00
Michal Simek
ac72bdc037 style(xilinx): fix AMD copyright format
There is missing comma in copyright line. It is better to have all
Copyrights align to the same style that's why fix it.

Change-Id: Ifc04b474e1a172a7243b073d944007cf17d76e87
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-04-24 14:46:41 +02:00
Joanna Farley
0aab76a4e3 Merge changes from topic "versal/xlat-v2" into integration
* changes:
  feat(versal): switch to xlat_v2
  fix(xilinx): remove asserts around arg0/arg1
2023-04-24 14:08:10 +02:00
Sandrine Bailleux
1dc77d43ef docs: split deprecated interfaces and drivers
Having a dedicated section for deprecated interfaces, and another one
for deprecated drivers, sounds cleaner.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Iaf65e9f4dabff89b9e86c17062656edd8c344016
2023-04-24 13:45:53 +02:00
Sandrine Bailleux
47801a6985 docs: extend deprecation policy
Our process documentation already mentions that if a platform is no
longer maintained, it is best to deprecate it to keep the project's
source tree clean and healthy.

The same argument stands for drivers or library interfaces so extend
this policy to those.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ieb235d6a1fb089343e0e1e3e5f36067552f2f8f0
2023-04-24 13:45:44 +02:00
Sandrine Bailleux
8f55cde216 docs: add a note about downstream platforms
Clarify that downstream platforms generally do not affect code
deprecation / removal decisions.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I44b979c4e67ee03537852769e96544e19137bda3
2023-04-24 13:45:06 +02:00
Chris Kay
26ad4a87e0 docs(juno): update SCP downloads link
Change-Id: Ibe2a1d2ec019333876a4f82b70fde0a10d667f7c
Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-04-21 14:25:05 +02:00
Manish Pandey
edee0430d4 Merge "fix(uuid): add missing #include directives" into integration 2023-04-21 14:24:12 +02:00
Yann Gautier
dee99f10b1 refactor(auth)!: unify REGISTER_CRYPTO_LIB
Have only one definition for REGISTER_CRYPTO_LIB macro, with all the
possible fields. Worst case adds 4 u64 to crypto_lib_desc.
While at it, correct some MISRA violations:
MC3R1.R12.1: (advisory) The precedence of operators within expressions
should be made explicit.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1342a20e6eef2354753182c2a81ff959e03e5c81
2023-04-21 09:46:01 +01:00
Yann Gautier
4ac5b3949d refactor(auth): replace plat_convert_pk
Following discussions in the reviews of the patch that introduced
plat_convert_pk() function [1], it was decided to deprecate it to
avoid weak function declaration.
A new optional function pointer convert_pk is added to crypto_lib_desc_t.
A new function crypto_mod_convert_pk() will either call
crypto_lib_desc.convert_pk() if it is defined, or do the same
as what was done by the weak function otherwise.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17174

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9358867f8bfd5e96b5ee238c066877da368e43c6
2023-04-21 09:46:01 +01:00
Yann Gautier
0ca7b32623 docs(auth): add auth_decrypt in CM chapter
The call to REGISTER_CRYPTO_LIB requires auth_decrypt function to be
provided. Add its prototype and update REGISTER_CRYPTO_LIB call.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id1f2a54867ffe5dec36e0bf22490d01858891585
2023-04-21 09:46:01 +01:00
Manish V Badarkhe
f1e693a775 feat(auth): compare platform and certificate ROTPK for authentication
Compared the full ROTPK with the ROTPK obtained from the certificate
when the platform supports full ROTPK instead of hash of ROTPK.

Additionally, changed the code to verify the ROTPK before relying on
it for signature verification.

Change-Id: I52bb9deb1a1dd5b184d3156bddad14c238692de7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-04-21 09:46:01 +01:00