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https://github.com/ARM-software/arm-trusted-firmware.git
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refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED
At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
parent
100f56d873
commit
88727fc3ec
7 changed files with 49 additions and 25 deletions
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@ -263,7 +263,7 @@ smc_args_t *tsp_smc_handler(uint64_t func,
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results[1] /= service_arg1 ? service_arg1 : 1;
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break;
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case TSP_CHECK_DIT:
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if (!is_armv8_4_dit_present()) {
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if (!is_feat_dit_supported()) {
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ERROR("DIT not supported\n");
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results[0] = 0;
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results[1] = 0xffff;
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@ -80,16 +80,6 @@ static void read_feat_pauth(void)
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#endif
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}
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/************************************************************
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* Feature : FEAT_DIT (Data Independent Timing Instructions)
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***********************************************************/
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static void read_feat_dit(void)
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{
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#if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS)
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feat_detect_panic(is_armv8_4_feat_dit_present(), "DIT");
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#endif
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}
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/************************************************
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* Feature : FEAT_MTE (Memory Tagging Extension)
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***********************************************/
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@ -178,7 +168,7 @@ void detect_arch_features(void)
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read_feat_pauth();
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/* v8.4 features */
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read_feat_dit();
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check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1);
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check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
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"AMUv1", 1, 2);
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check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
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@ -92,6 +92,24 @@ static inline bool is_feat_sys_reg_trace_supported(void)
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return read_feat_coptrc_id_field() != 0U;
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}
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static inline unsigned int read_feat_dit_id_field(void)
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{
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return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_DIT);
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}
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static inline bool is_feat_dit_supported(void)
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{
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if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
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return false;
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}
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if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
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return true;
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}
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return read_feat_dit_id_field() != 0U;
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}
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static inline bool is_feat_spe_supported(void)
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{
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/* FEAT_SPE is AArch64 only */
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@ -89,12 +89,6 @@ static inline bool is_armv8_3_pauth_present(void)
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is_feat_pacqarma3_present());
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}
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static inline bool is_armv8_4_dit_present(void)
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{
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return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) &
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ID_AA64PFR0_DIT_MASK) == 1U;
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}
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static inline bool is_armv8_4_ttst_present(void)
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{
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return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
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@ -515,13 +509,22 @@ static inline bool is_armv8_2_feat_ras_present(void)
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ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED);
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}
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/**************************************************************************
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* Function to identify the presence of FEAT_DIT (Data Independent Timing)
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*************************************************************************/
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static inline bool is_armv8_4_feat_dit_present(void)
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static unsigned int read_feat_dit_id_field(void)
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{
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return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) &
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ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED);
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT);
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}
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static inline bool is_feat_dit_supported(void)
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{
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if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
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return false;
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}
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if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
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return true;
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}
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return read_feat_dit_id_field() != 0U;
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}
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static inline unsigned int read_feat_tracever_id_field(void)
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@ -243,14 +243,20 @@
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* register value for DIT.
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*/
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#if ENABLE_FEAT_DIT
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#if ENABLE_ASSERTIONS
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#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
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#if ENABLE_FEAT_DIT > 1
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cbz x0, 1f
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#else
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cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
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ASM_ASSERT(eq)
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#endif
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#endif /* ENABLE_ASSERTIONS */
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mov x0, #DIT_BIT
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msr DIT, x0
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1:
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#endif
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.endm
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@ -553,8 +553,14 @@ endfunc fpregs_context_restore
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* always enable DIT in EL3
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*/
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#if ENABLE_FEAT_DIT
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#if ENABLE_FEAT_DIT == 2
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mrs x8, id_aa64pfr0_el1
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and x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT)
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cbz x8, 1f
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#endif
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mov x8, #DIT_BIT
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msr DIT, x8
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1:
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#endif /* ENABLE_FEAT_DIT */
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.endm /* set_unset_pstate_bits */
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@ -70,6 +70,7 @@ endif
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ENABLE_TRBE_FOR_NS := 2
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ENABLE_SYS_REG_TRACE_FOR_NS := 2
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ENABLE_FEAT_CSV2_2 := 2
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ENABLE_FEAT_DIT := 2
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ENABLE_FEAT_PAN := 2
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ENABLE_FEAT_VHE := 2
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CTX_INCLUDE_NEVE_REGS := 2
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