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88727fc3ec
At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
286 lines
8.9 KiB
C
286 lines
8.9 KiB
C
/*
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* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <bl32/tsp/tsp.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/spinlock.h>
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#include <plat/common/platform.h>
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#include <platform_tsp.h>
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#include "tsp_private.h"
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#include <platform_def.h>
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/*******************************************************************************
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* TSP main entry point where it gets the opportunity to initialize its secure
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* state/applications. Once the state is initialized, it must return to the
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* SPD with a pointer to the 'tsp_vector_table' jump table.
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******************************************************************************/
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uint64_t tsp_main(void)
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{
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NOTICE("TSP: %s\n", version_string);
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NOTICE("TSP: %s\n", build_message);
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INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
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INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
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uint32_t linear_id = plat_my_core_pos();
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/* Initialize the platform */
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tsp_platform_setup();
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/* Initialize secure/applications state here */
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tsp_generic_timer_start();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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tsp_stats[linear_id].cpu_on_count++;
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_on_count);
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return (uint64_t) &tsp_vector_table;
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}
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/*******************************************************************************
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* This function performs any remaining book keeping in the test secure payload
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* after this cpu's architectural state has been setup in response to an earlier
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* psci cpu_on request.
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******************************************************************************/
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smc_args_t *tsp_cpu_on_main(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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/* Initialize secure/applications state here */
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tsp_generic_timer_start();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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tsp_stats[linear_id].cpu_on_count++;
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INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_on_count);
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/* Indicate to the SPD that we have completed turned ourselves on */
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return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
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}
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/*******************************************************************************
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* This function performs any remaining book keeping in the test secure payload
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* before this cpu is turned off in response to a psci cpu_off request.
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******************************************************************************/
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smc_args_t *tsp_cpu_off_main(uint64_t arg0,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint32_t linear_id = plat_my_core_pos();
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/*
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* This cpu is being turned off, so disable the timer to prevent the
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* secure timer interrupt from interfering with power down. A pending
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* interrupt will be lost but we do not care as we are turning off.
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*/
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tsp_generic_timer_stop();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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tsp_stats[linear_id].cpu_off_count++;
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INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_off_count);
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/* Indicate to the SPD that we have completed this request */
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return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
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}
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/*******************************************************************************
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* This function performs any book keeping in the test secure payload before
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* this cpu's architectural state is saved in response to an earlier psci
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* cpu_suspend request.
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******************************************************************************/
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smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint32_t linear_id = plat_my_core_pos();
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/*
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* Save the time context and disable it to prevent the secure timer
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* interrupt from interfering with wakeup from the suspend state.
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*/
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tsp_generic_timer_save();
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tsp_generic_timer_stop();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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tsp_stats[linear_id].cpu_suspend_count++;
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_suspend_count);
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/* Indicate to the SPD that we have completed this request */
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return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
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}
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/*******************************************************************************
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* This function performs any book keeping in the test secure payload after this
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* cpu's architectural state has been restored after wakeup from an earlier psci
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* cpu_suspend request.
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******************************************************************************/
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smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint32_t linear_id = plat_my_core_pos();
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/* Restore the generic timer context */
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tsp_generic_timer_restore();
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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tsp_stats[linear_id].cpu_resume_count++;
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INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
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read_mpidr(), max_off_pwrlvl);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count,
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tsp_stats[linear_id].cpu_resume_count);
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/* Indicate to the SPD that we have completed this request */
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return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
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}
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/*******************************************************************************
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* TSP fast smc handler. The secure monitor jumps to this function by
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* doing the ERET after populating X0-X7 registers. The arguments are received
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* in the function arguments in order. Once the service is rendered, this
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* function returns to Secure Monitor by raising SMC.
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******************************************************************************/
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smc_args_t *tsp_smc_handler(uint64_t func,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7)
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{
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uint128_t service_args;
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uint64_t service_arg0;
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uint64_t service_arg1;
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uint64_t results[2];
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uint32_t linear_id = plat_my_core_pos();
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u_register_t dit;
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/* Update this cpu's statistics */
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tsp_stats[linear_id].smc_count++;
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tsp_stats[linear_id].eret_count++;
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INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
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((func >> 31) & 1) == 1 ? "fast" : "yielding",
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func);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
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tsp_stats[linear_id].smc_count,
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tsp_stats[linear_id].eret_count);
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/* Render secure services and obtain results here */
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results[0] = arg1;
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results[1] = arg2;
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/*
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* Request a service back from dispatcher/secure monitor.
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* This call returns and thereafter resumes execution.
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*/
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service_args = tsp_get_magic();
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service_arg0 = (uint64_t)service_args;
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service_arg1 = (uint64_t)(service_args >> 64U);
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#if CTX_INCLUDE_MTE_REGS
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/*
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* Write a dummy value to an MTE register, to simulate usage in the
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* secure world
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*/
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write_gcr_el1(0x99);
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#endif
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/* Determine the function to perform based on the function ID */
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switch (TSP_BARE_FID(func)) {
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case TSP_ADD:
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results[0] += service_arg0;
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results[1] += service_arg1;
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break;
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case TSP_SUB:
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results[0] -= service_arg0;
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results[1] -= service_arg1;
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break;
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case TSP_MUL:
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results[0] *= service_arg0;
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results[1] *= service_arg1;
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break;
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case TSP_DIV:
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results[0] /= service_arg0 ? service_arg0 : 1;
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results[1] /= service_arg1 ? service_arg1 : 1;
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break;
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case TSP_CHECK_DIT:
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if (!is_feat_dit_supported()) {
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ERROR("DIT not supported\n");
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results[0] = 0;
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results[1] = 0xffff;
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break;
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}
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dit = read_dit();
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results[0] = dit == service_arg0;
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results[1] = dit;
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/* Toggle the dit bit */
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write_dit(service_arg0 != 0U ? 0 : DIT_BIT);
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break;
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default:
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break;
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}
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return set_smc_args(func, 0,
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results[0],
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results[1],
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0, 0, 0, 0);
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}
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