Commit graph

11359 commits

Author SHA1 Message Date
AlexeiFedorov
8e51cccaef fix(rmmd): return X4 output value
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I92907ac3ff3bac8554643ae7c198a4a758c38cb3
2022-09-28 15:11:03 +02:00
Jayanth Dodderi Chidanand
066450abf3 fix(tc): resolve the static-checks errors
Converted the space indentation to tabs to fix the
errors listed under tf-static-checks CI job.

Change-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2022-09-28 13:48:12 +01:00
Raef Coles
3125901923 feat(rss): add new comms protocols
The current comms protocol (where arguments and return data is embedded
into the MHU message) is now protocol v0. Protocol v1 embeds pointers
into the message, and has the RSS retrieve the data via DMA.

Change-Id: I08d7f09c4eaea673769fde9eee194447a99f1b78
Signed-off-by: Raef Coles <raef.coles@arm.com>
2022-09-28 13:38:02 +01:00
Manish V Badarkhe
7c49438874 fix(semihosting): fix seek call failure check
The code checks that the semihosting seek call return value is not
zero instead of a negative value when there is an error condition.
This defect has been fixed.

In [1], possible return values for semihosting seek calls are
mentioned.

[1]: https://github.com/ARM-software/abi-aa/blob/main/semihosting/
semihosting.rst#sys-seek-0x0a

Change-Id: I70f09e98323e9c5bf4eeda322ac065e855e256fc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-09-28 11:53:42 +01:00
Chunlei Xu
18af644279 feat(ls1043ardb): update ddr configure for ls1043ardb-pd
DDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R.
New ddr configure is compatible with both pd and old version of ls1043ardb.

Signed-off-by: Chunlei Xu <chunlei.xu@nxp.com>
Change-Id: I714c091a2cf15046438d0723fb55a4410c386ef4
2022-09-28 16:58:15 +08:00
Jorge Troncoso
c5862af72d chore(libc): clean up includes in lib/libc/printf.c
stddef.h is needed for the definition of size_t
stdio.h is needed for the declaration of putchar

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I72dac843dbbfc440cff0f9e9d13669b78a812abc
2022-09-27 22:50:54 -07:00
Joanna Farley
58aebb6a53 Merge "fix(libc): pri*ptr macros for aarch64" into integration 2022-09-28 01:19:28 +02:00
Sandrine Bailleux
0f2ab75fa3 Merge "feat(tc): add RTC PL031 device tree node" into integration 2022-09-27 13:03:54 +02:00
Manish V Badarkhe
14ec900a42 Merge "docs(maintainers): add myself as TC code owner" into integration 2022-09-27 11:42:46 +02:00
Anders Dellien
8fecda3c8a docs(maintainers): add myself as TC code owner
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic67334bf1a979cb7b7355d0dcca7eb94752c4611
2022-09-27 09:47:54 +01:00
K
d307229d75 fix(libc): pri*ptr macros for aarch64
This fix solves problems with using PRI*PTR on aarch64 like so:
error: format '%x' expects argument of type 'unsigned int', but
argument 3 has type 'uintptr_t' {aka 'long unsigned int'}

Change-Id: I135d3e5cea5459f138b20331b5e9472e2e9e566c
Signed-off-by: K <kayo@illumium.org>
2022-09-27 09:19:32 +02:00
HariBabu Gattem
cdb62114cf fix(zynqmp): resolve misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Change-Id: I3779f7b6e074e33cb66ace3bef2117029badce1e
2022-09-26 12:13:00 +02:00
Sandrine Bailleux
d8d0ea9a7f Merge "docs(fwu): update firmware update design" into integration 2022-09-26 11:02:51 +02:00
Joanna Farley
2aaed86080 Merge "refactor(libc): clean up dependencies in libc" into integration 2022-09-23 17:24:01 +02:00
Yann Gautier
14a070408d feat(stm32mp1): add early console in SP_min
Allow early console to be used at the beginning of SP_min, before
the clocks and UART have been reconfigured.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I53d66938d42fcec830d9b81e5ef62b3790d0c3b3
2022-09-23 15:17:43 +02:00
Yann Gautier
5223d88032 feat(st): properly manage early console
The new flag STM32MP_RECONFIGURE_CONSOLE is managed in platform.mk.
It is used in stm32mp_setup_early_console() when calling
plat_crash_console_init(). This call is also under:
"#if defined(IMAGE_BL2)"
as this crash console init shouldn't be done by default in BL32.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ib6b89db83d80095b662a2016e18ceb3fa8668435
2022-09-23 15:17:43 +02:00
Yann Gautier
ea69dcdc73 feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
If the flag STM32MP_RECONFIGURE_CONSOLE is set in BL32, the UART init
should be skipped if the UART clock is set to zero. This will be used
when configuring the default console, after an early console has been
configured.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Icbc640c7bdd6342f9c3ec1586a0d0c64127b18b8
2022-09-23 15:17:43 +02:00
Yann Gautier
156709ddde docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured in BL2.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b28ff489479ab04a2fade027933524cdd36e959
2022-09-23 15:17:43 +02:00
Yann Gautier
00606df012 feat(st): add trace for early console
When the early console is configured with STM32MP_EARLY_CONSOLE,
display a message indicating it is enabled.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iafdfa5afef27eba823d707841853a8a46de0b42d
2022-09-23 15:17:43 +02:00
Yann Gautier
484e846a03 fix(stm32mp1): enable crash console in FIQ handler
When a FIQ occurs and is trapped by SP_min, it is an unrecoverable
error. As kernel may have switched the UART console off, we should
re-enable it with plat_crash_console_init() for those failing states.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib02e1271b6213f8e383a062b74494abf8826188f
2022-09-23 15:17:43 +02:00
Patrick Delaunay
d99998f76e feat(st-uart): add initialization with the device tree
Add the pincontrol configuration and clock enable in UART driver
with information found in the device tree.

This patch avoids an issue on STM32MP13x platform because the UART
configuration is reset by the ROM code for UART serial boot
(STM32MP_UART_PROGRAMMER=1).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I575fd0e1026b857059abcfd4a3166eb3a239e1fd
2022-09-23 15:17:43 +02:00
Patrick Delaunay
7d197d6281 refactor(stm32mp1): move DT_UART_COMPAT in include file
Move the definition of DT_UART_COMPAT in stm32mp1_def.h to be used
in several files.

Change-Id: I74d0350bcd971df9b15697f2b9ec04061d6a7656
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-23 15:17:43 +02:00
Patrick Delaunay
4b2f23e55f feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.

To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
2022-09-23 15:17:43 +02:00
Patrick Delaunay
32f2ca04bf fix(stm32mp1): update the FIP load address for serial boot
Update the FIP load address and size for serial boot to support
product with a DDR size = 128MB
1/ Move the FIP location at the end of the first 128MB
2/ Reduce the DWL_BUFFER_SIZE to 16MB, to be coherent with the value
   indicated in USB enumeration
   - for STM32MP13x: "@SSBL /0x03/1*16Me"
   - for STM32MP15x: "@Partition3 /0x03/1*16Me"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id93bf00c64832c17426bfd78e060861275677ecc
2022-09-23 15:17:43 +02:00
Patrick Delaunay
e7705e9afd refactor(st): configure baudrate for UART programmer
Add the possibility to configure the UART baudrate; reused the
console configuration, defined in STM32MP_UART_BAUDRATE.

The default value remains 115200.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifcf2b36e8ac929265405bc88e824ee78be3b5bbb
2022-09-23 15:17:43 +02:00
Patrick Delaunay
1258189515 refactor(st-uart): compute the over sampling dynamically
The parameter over_sampling of stm32_uart_init_s is not required
as it can be computed dynamically from clock rate of the serial
device and the requested baudrate.

Oversampling by 8 is allowed only for higher speed
(up to clock_rate / 8) to reduce the maximum receiver tolerance
to clock deviation.

This patch update the driver, the serial init struct and the
only user, the stm32cubeprogrammer over uart support.

Change-Id: I422731089730a288defeb7fa49886db65d0902b2
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-23 15:17:43 +02:00
Manish V Badarkhe
278bc857d8 Merge changes from topic "bl31_in_sram" into integration
* changes:
  feat(sgi): remove override for `ARM_BL31_IN_DRAM` build-option
  feat(sgi): configure SRAM and BL31 size for sgi platform
2022-09-23 13:32:09 +02:00
Olivier Deprez
aef9b0da2a Merge "fix(bl31): fix validate_el3_interrupt_rm preprocessor usage" into integration 2022-09-23 10:14:13 +02:00
Rohit Mathew
a371327ba9 feat(sgi): remove override for ARM_BL31_IN_DRAM build-option
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8d79969c003a984675cbe705de890b51a1f7f4ea
2022-09-22 20:44:58 +01:00
Rohit Mathew
8fd820ffb9 feat(sgi): configure SRAM and BL31 size for sgi platform
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I11c2672a1089f24a9fafcf6555b8e1d52032cfde
2022-09-22 16:58:18 +01:00
Manish Pandey
602394507f Merge changes from topic "mediatek upstream" into integration
* changes:
  refactor(mt8188): move platform_def.h to mt8188/include
  feat(mt8188): add MCUSYS support
  feat(mt8188): add armv8.2 support
  feat(mt8188): add DFD control in SiP service
  feat(mt8188): add EMI MPU basic drivers
  feat(mt8188): add DCM driver
  feat(mt8188): add reset and poweroff functions
  feat(mediatek): add more flexibility of mtk_pm.c
  feat(mediatek): add more options for build helper
  feat(mt8188): add LPM driver support
  feat(mt8188): apply ERRATA for CA-78
  fix(mediatek): remove unused cold_boot.[c|h]
  fix(mediatek): wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE
  feat(mt8186): add EMI MPU support for SCP and DSP
2022-09-22 16:31:49 +02:00
Bo-Chen Chen
a64d9f442e refactor(mt8188): move platform_def.h to mt8188/include
It is more suitable to place platform_def.h in mt8188/include.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I35720690ff4f2ca99c9430edb8bbe17edf9aefb9
2022-09-22 19:26:15 +08:00
Edward-JW Yang
4cc1ff7ef2 feat(mt8188): add MCUSYS support
Add MCUSYS drivers support for MT8188.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I84107702a9fd021c37d2997ad25b321a483a1a66
2022-09-22 19:26:15 +08:00
Edward-JW Yang
45711e4e16 feat(mt8188): add armv8.2 support
Add armv8.2 support for MT8188.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I0ac865949ba864fb207ee1f0937092cbabd550de
2022-09-22 19:26:15 +08:00
Fengquan Chen
7079a942bd feat(mt8188): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.

TEST=build pass.
BUG=b:244216434

Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com>
Change-Id: I468036131e941a46bc1ec12d33105146000730d8
2022-09-22 19:26:15 +08:00
Dawei Chien
8454f0d65e feat(mt8188): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8188 supports 32 regions and 16 domains.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Change-Id: I9bbeb355665401cc71dda6db22157d9d751570d1
2022-09-22 19:26:15 +08:00
Garmin Chang
bc9410e237 feat(mt8188): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.

Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I131354d72bbc190af504e9639bcc85a720e2bb17
2022-09-22 19:26:15 +08:00
Rex-BC Chen
a72b9e7754 feat(mt8188): add reset and poweroff functions
- Add mtk_pm_system_reset_cros() for cros reset.
- Add mtk_pm_system_off_cros() for cros power-off.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4117f6080e282551b37a936a490ab7b37ac31827
2022-09-22 19:26:15 +08:00
Edward-JW Yang
6ca2046ef1 feat(mediatek): add more flexibility of mtk_pm.c
To use power manager function more easier, we add some drivers to let
the implementation easier.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: Ibc6e1680c4534592ed37de49da39b6667f468ea1
2022-09-22 19:26:15 +08:00
Edward-JW Yang
5b95e439c7 feat(mediatek): add more options for build helper
To support more LPM feature, we add more options for build helper.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I17eeedbe0674e321f1891074ba0c72d858841dae
2022-09-22 19:26:15 +08:00
Bo-Chen Chen
f604e4ef6e feat(mt8188): add LPM driver support
Add LPM drivers and create rules.mk for makefile.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0bfb99a4a763e7ca93260f62d1ced184259acb39
2022-09-22 19:26:15 +08:00
Bo-Chen Chen
abb995abbe feat(mt8188): apply ERRATA for CA-78
Apply ERRATA_A78_2376745 and ERRATA_A78_2395406 for CA-78.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4575e83025af971a669dc1f8561cf19e1fdac469
2022-09-22 19:26:15 +08:00
Bo-Chen Chen
8cd3b693d6 fix(mediatek): remove unused cold_boot.[c|h]
We are not using cold_boot.[c|h] for mt8188, so remove them first.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I721aca37d5fb422f274bb1ab46150e1eddf7c480
2022-09-22 19:26:15 +08:00
Bo-Chen Chen
24476b2e61 fix(mediatek): wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE
We should wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE to avoid
build error.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idfd760fbb7c782d4fc9de674d86a7123e0129c0d
2022-09-22 19:26:15 +08:00
Allen-KH Cheng
3d4b6f9324 feat(mt8186): add EMI MPU support for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x5109FFFF.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204229221
TEST=build pass

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I6a7d2eafaaa7a558829a0d741dfb3307885e3b98
2022-09-22 19:26:15 +08:00
Claus Pedersen
885e268304 refactor(libc): clean up dependencies in libc
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
  "platform_def.h" from assert.h and adding "common/debug.h"
  where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
  Instead removing assert with expression, as this
  does not provide additional information.

Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568
2022-09-22 13:23:49 +02:00
Manish Pandey
93910a7487 Merge "feat(pauth): add/modify helpers to support QARMA3" into integration 2022-09-22 11:59:39 +02:00
Manish V Badarkhe
2c20c24211 Merge "fix(synquacer): increase size of BL33" into integration 2022-09-22 10:46:06 +02:00
Joanna Farley
f530821abf Merge "feat(versal_net): add support for QEMU COSIM platform" into integration 2022-09-22 10:22:10 +02:00
Joanna Farley
ae69686b58 Merge "docs(maintainers): update xilinx record to cover docs" into integration 2022-09-22 10:15:38 +02:00