Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 09:34:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

feat(ls1043ardb): update ddr configure for ls1043ardb-pd

Browse source 
DDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R.
New ddr configure is compatible with both pd and old version of ls1043ardb.

Signed-off-by: Chunlei Xu <chunlei.xu@nxp.com>
Change-Id: I714c091a2cf15046438d0723fb55a4410c386ef4
This commit is contained in:
Chunlei Xu 2022-09-28 16:58:15 +08:00
parent d8d0ea9a7f
commit 18af644279
1 changed files with 17 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
View file

@ -85,32 +85,36 @@ int ddr_board_options(struct ddr_info *priv)
return 0;
}
/* DDR model number: MT40A512M8HX-093E */
/* DDR model number: MT40A1G8SA-062E:R */
struct dimm_params ddr_raw_timing = {
.n_ranks = U(1),
.rank_density = ULL(2147483648),
.capacity = ULL(2147483648),
.primary_sdram_width = U(32),
.n_row_addr = U(15),
.ec_sdram_width = U(4),
.rdimm = U(0),
.mirrored_dimm = U(0),
.n_row_addr = U(16),
.n_col_addr = U(10),
.bank_group_bits = U(2),
.edc_config = U(2),
.burst_lengths_bitmask = U(0x0c),
.tckmin_x_ps = 938,
.tckmax_ps = 1500,
.caslat_x = U(0x000DFA00),
.tckmin_x_ps = 625,
.tckmax_ps = 2200,
.caslat_x = U(0x0001FFE00),
.taa_ps = 13500,
.trcd_ps = 13500,
.trp_ps = 13500,
.tras_ps = 33000,
.trc_ps = 46500,
.tras_ps = 32000,
.trc_ps = 45500,
.twr_ps = 15000,
.trfc1_ps = 260000,
.trfc2_ps = 160000,
.trfc4_ps = 110000,
.trfc1_ps = 350000,
.trfc2_ps = 260000,
.trfc4_ps = 160000,
.tfaw_ps = 21000,
.trrds_ps = 3700,
.trrdl_ps = 5300,
.tccdl_ps = 5355,
.trrds_ps = 3000,
.trrdl_ps = 4900,
.tccdl_ps = 5000,
.refresh_rate_ps = U(7800000),
.rc = U(0x1f),
};