Commit graph

11828 commits

Author SHA1 Message Date
Manish Pandey
76a91d8769 refactor(el3_runtime): remove unnecessary assembly macros
Following macros removed
  - handle_async_ea : It duplicates "check_and_unmask_ea" functionality
  - check_if_serror_from_EL3: This macro is small and called only once,
    replace this macro with instructions at the caller.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Id7eec6263ec23cc8792139f491c563f616fd3618
2023-01-10 18:02:36 +00:00
Madhukar Pappireddy
0e4655f828 Merge "docs(changelog): add console scope" into integration 2023-01-09 16:45:52 +01:00
Madhukar Pappireddy
bacfff8bb0 Merge "fix(libc): properly define SCHAR_MIN" into integration 2023-01-09 16:14:42 +01:00
Manish V Badarkhe
c9c752e9ff Merge "docs(maintainers): update maintainers for total compute" into integration 2023-01-09 15:32:16 +01:00
Rupinderjit Singh
08f439f417 docs(maintainers): update maintainers for total compute
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: I64e7b036f404da110339d9013aa5c17ed8bf100f
2023-01-09 13:44:14 +00:00
Manish V Badarkhe
36ec4c7541 Merge "fix(plat/tc): increase TC_TZC_DRAM1_SIZE" into integration 2023-01-09 14:15:49 +01:00
Yann Gautier
3c78829035 docs(changelog): add console scope
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie9426509ee4f0a4c4f0fe0296d7a7378cc8828f5
2023-01-06 17:06:10 +01:00
Madhukar Pappireddy
51920f0f36 Merge "fix(fconf): make struct fconf_populator static" into integration 2023-01-06 16:44:20 +01:00
Yann Gautier
06c01b085f fix(libc): properly define SCHAR_MIN
SCHAR_MIN definition should use SCHAR_MAX, and not itself.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If8c1751a381dac50fe3ec5fdf19d6a4918470b58
2023-01-06 14:22:09 +01:00
Yann Gautier
40e740dc14 fix(fconf): make struct fconf_populator static
In FCONF_REGISTER_POPULATOR macro, add static for the fconf_populator
struct. This avoids this kind of sparse warning:
plat/st/common/stm32mp_fconf_io.c:181:1: warning:
 symbol 'stm32mp_io__populator' was not declared. Should it be static?

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Icaa7da3079e82497e112585150f6348ef2ebf5e6
2023-01-06 10:39:11 +01:00
Olivier Deprez
be737af7c8 Merge "feat(mt8188): update INFRA IOMMU enable flow" into integration 2023-01-06 09:38:25 +01:00
Chengci.Xu
98415e1a80 feat(mt8188): update INFRA IOMMU enable flow
IOMMU kernel driver has changed the function parameters, so update
IOMMU TF-A driver to be consistent with it.

Change-Id: I2adda69bdbdc31833781fac5e6c1f4b10da161be
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
2023-01-06 09:42:33 +08:00
Manish Pandey
0c6a085402 Merge changes from topic "fvp_trap_rng" into integration
* changes:
  feat(fvp): emulate trapped RNDR
  feat(el3-runtime): introduce system register trap handler
2023-01-04 18:51:40 +01:00
Manish Pandey
e2dcf8b4fe Merge "refactor(trng): discarding the used entropy bits" into integration 2023-01-04 11:41:46 +01:00
Arunachalam Ganapathy
7e3f6a87d7 fix(plat/tc): increase TC_TZC_DRAM1_SIZE
Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size.
Update OP-TEE reserved memory range in DTS

Change-Id: Iad433c3c155f28860b15bde2398df653487189dd
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
2023-01-04 15:03:51 +05:30
Sandrine Bailleux
ef27dd231e Merge "refactor(auth): avoid parsing signature algorithm twice" into integration 2023-01-04 10:16:10 +01:00
Sandrine Bailleux
40fd1c024d Merge changes I794d2927,Ie33205fb,Ifdbe3b4c into integration
* changes:
  refactor(auth): do not include SEQUENCE tag in saved extensions
  fix(auth): reject junk after certificates
  fix(auth): require bit strings to have no unused bits
2023-01-03 17:55:02 +01:00
Demi Marie Obenour
ce882b5364 refactor(auth): do not include SEQUENCE tag in saved extensions
This makes the code a little bit smaller.  No functional change
intended.

Change-Id: I794d2927fcd034a79e29c9bba1f8e4410203f547
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-01-03 17:49:24 +01:00
Demi Marie Obenour
ca34dbc0cd fix(auth): reject junk after certificates
Certificates must not allow trailing junk after them.

Change-Id: Ie33205fb051fc63af5b72c326822da7f62eec1d1
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-01-03 17:49:16 +01:00
Demi Marie Obenour
8816dbb381 fix(auth): require bit strings to have no unused bits
This is already checked by the crypto module or by mbedTLS, but checking
it in the X.509 parser is harmless.

Change-Id: Ifdbe3b4c6d04481bb8e93106ee04b49a70f50d5d
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2023-01-03 17:48:51 +01:00
Sandrine Bailleux
2439a80886 Merge changes Ia748b6ae,Id8a48e14,Id25ab231,Ie26eed8a,Idf48f716, ... into integration
* changes:
  refactor(auth): partially validate SubjectPublicKeyInfo early
  fix(auth): reject padding after BIT STRING in signatures
  fix(auth): reject invalid padding in digests
  fix(auth): require at least one extension to be present
  fix(auth): forbid junk after extensions
  fix(auth): only accept v3 X.509 certificates
2023-01-03 17:48:09 +01:00
Manish Pandey
a95a451b0a Merge changes from topic "st_fix_sparse_warnings" into integration
* changes:
  fix(st-crypto): remove platdata functions
  fix(st-crypto): set get_plain_pk_from_asn1() static
  fix(stm32mp1): add missing platform.h include
  fix(st): make metadata_block_spec static
2023-01-03 14:27:07 +01:00
Demi Marie Obenour
63cc49d0aa refactor(auth): avoid parsing signature algorithm twice
Since the two instances of the signature algorithm in a certificate must
be bitwise identical, it is not necessary to parse both of them.
Instead, it suffices to parse one of them, and then check that the other
fits in the remaining buffer space and is equal to the first.

Change-Id: Id0a0663165f147879ac83b6a540378fd4873b0dd
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 19:18:22 -05:00
Demi Marie Obenour
94c0cfbb82 refactor(auth): partially validate SubjectPublicKeyInfo early
This reduces the likelihood of future problems later.

Change-Id: Ia748b6ae31a7a48f17ec7f0fc08310a50cd1b135
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 18:41:10 -05:00
Demi Marie Obenour
a8c8c5ef2a fix(auth): reject padding after BIT STRING in signatures
It is forbidden by ASN.1 DER.

Change-Id: Id8a48e14bb8a1a17a6481ea3fde0803723c05e31
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 18:41:10 -05:00
Demi Marie Obenour
f47547b354 fix(auth): reject invalid padding in digests
Digests must not have padding after the SEQUENCE or OCTET STRING.

Change-Id: Id25ab23111781f8c8a97c2c3c8edf1cc4a4384c0
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 18:41:10 -05:00
Demi Marie Obenour
72460f50e2 fix(auth): require at least one extension to be present
X.509 and RFC5280 allow omitting the extensions entirely, but require
that if the extensions field is present at all, it must contain at least
one certificate.  TF-A already requires the extensions to be present,
but allows them to be empty.  However, a certificate with an empty
extensions field will always fail later on, as the extensions contain
the information needed to validate the next stage in the boot chain.
Therefore, it is simpler to require the extension field to be present
and contain at least one extension.  Also add a comment explaining why
the extensions field is required, even though it is OPTIONAL in the
ASN.1 syntax.

Change-Id: Ie26eed8a7924bf50937a6b27ccdf7cc9a390588d
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 18:41:10 -05:00
Demi Marie Obenour
fd37982a19 fix(auth): forbid junk after extensions
The extensions must use all remaining bytes in the TBSCertificate.

Change-Id: Idf48f7168e146d050ba62dbc732638946fcd6c92
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 18:41:10 -05:00
Demi Marie Obenour
e9e4a2a6fd fix(auth): only accept v3 X.509 certificates
v1 and v2 are forbidden as at least one extension is required.  Instead
of actually parsing the version number, just compare it with a
hard-coded string.

Change-Id: Ib8fd34304a0049787db77ec8c2359d0930cd4ba1
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
2022-12-29 18:41:10 -05:00
Bipin Ravi
af467fc3d3 Merge "fix(qemu-sbsa): enable SVE and SME" into integration 2022-12-22 23:38:58 +01:00
Manish V Badarkhe
8c276af390 Merge changes Ia14738de,I6f4cffdc into integration
* changes:
  fix(tc): change the properties of optee reserved memory
  feat(tc): use smmu 700
2022-12-22 12:53:04 +01:00
Madhukar Pappireddy
c3c30ff88e Merge "fix(cpus): workaround for Neoverse N2 erratum 2743089" into integration 2022-12-21 17:27:21 +01:00
Bipin Ravi
1ee7c8232c fix(cpus): workaround for Neoverse N2 erratum 2743089
Neoverse N2 erratum 2743089 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Idec862226bd32c91374a8bbd5d73d7ee480a34d9
2022-12-21 16:35:39 +01:00
Madhukar Pappireddy
e7abef9036 Merge changes I0362da46,I8ee7c16c into integration
* changes:
  fix(cpus): workaround for Cortex-A78 erratum 2772019
  fix(cpus): workaround for Neoverse V1 erratum 2743093
2022-12-21 16:01:16 +01:00
Andre Przywara
1ae75529bc feat(fvp): emulate trapped RNDR
When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the real CPU instructions, potentially conditioning the
results, or use rate-limiting or filtering to protect the hardware
entropy pool. Another possiblitiy would be to use some platform specific
TRNG device to get entropy and returning this.

To demonstrate platform specific usage, add a demo implementation for the
FVP: It will execute the actual CPU instruction and just return the
result. This should serve as reference code to implement platform specific
policies.

We change the definition of read_rndr() and read_rndrrs() to use the
alternative sysreg encoding, so that all assemblers can handle that.

Add documentation about the new platform specific RNG handler function.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ibce817b3b06ad20129d15531b81402e3cc3e9a9e
2022-12-21 12:59:36 +00:00
Andre Przywara
ccd81f1e09 feat(el3-runtime): introduce system register trap handler
At the moment we only handle SMC traps from lower ELs, but ignore any
other synchronous traps and just panic.
To cope with system register traps, which we might need to emulate,
introduce a C function to handle those traps, and wire that up in the
exception handler to be called.

We provide a dispatcher function (in C), that will call platform
specific implementation for certain (classes of) system registers.
For now this is empty.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: If147bcb49472eb02791498700300926afbcf75ff
2022-12-21 10:25:25 +00:00
Bipin Ravi
b10afcce5f fix(cpus): workaround for Cortex-A78 erratum 2772019
Cortex-A78 erratum 2772019 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0362da463eca777aa7a385bcdeb39b8549799f02
2022-12-20 14:29:33 -06:00
Bipin Ravi
31747f057b fix(cpus): workaround for Neoverse V1 erratum 2743093
Neoverse V1 erratum 2743093 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401781/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8ee7c16c14c4fd6ee35d20c855273ecfce0d1b32
2022-12-20 14:17:20 -06:00
Olivier Deprez
f4d8ed50d2 Merge "fix(el3-spmc): report execution state in partition info get" into integration 2022-12-20 17:30:16 +01:00
Sandrine Bailleux
15a6c959de Merge "feat(tc): add delegated attest and measurement tests" into integration 2022-12-20 15:58:06 +01:00
Davidson K
2fff46c80f fix(tc): change the properties of optee reserved memory
make it part of the restricted dma pool to ensure it is not used for
general dma operations.

Change-Id: Ia14738de70b4d7719d7460ed8d16e727aea8d8c4
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
2022-12-20 12:01:05 +01:00
Davidson K
ed80eab6a6 feat(tc): use smmu 700
Enable smmu for gpu and dpu

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I6f4cffdc835dc542904b0a15b1db9a3382b78c08
2022-12-20 12:00:57 +01:00
Manish Pandey
01617e0bee Merge "fix(gic): wrap cache enabled assert under plat_can_cmo" into integration 2022-12-19 11:44:45 +01:00
Sandrine Bailleux
ff4a2c17eb Merge "fix(intel): add mailbox error return status for FCS_DECRYPTION" into integration 2022-12-19 08:37:23 +01:00
Manish V Badarkhe
6952ce49c2 Merge "fix(arm): arm_rotpk_header undefined reference" into integration 2022-12-17 11:44:21 +01:00
laurenw-arm
95302e4b23 fix(arm): arm_rotpk_header undefined reference
Moving ARM_ROTPK_S to default to arm_dev_rotpk.S as it was not being
set for Juno cryptocell and this should be the value in most cases.

Change-Id: I56a5a4e61f1ca728b87322b0b09a0d73ed1d5ee0
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2022-12-16 17:17:20 +00:00
Mate Toth-Pal
25dd2172ae feat(tc): add delegated attest and measurement tests
This patch adds Delegated Attestation and Measured Boot tests to the
plat/arm/board/tc platform.
The test suite can be activated by adding the build time option
`PLATFORM_TEST=1` to the make command. In this case the boot sequence is
not finished, plat_error_handler is called after the tests are run
(regardless of the test result.)

The actual test code is coming from the Trusted-Firmware-M project. Some
of the files of the tf-m-tests and tf-m-extras repo are linked to the
BL31 image.

Versions used for testing:
https://git.trustedfirmware.org/TF-M/tf-m-tests
    614e8c358377e4146e8ee13d1246e59d01b4bf1b

https: //git.trustedfirmware.org/TF-M/tf-m-extras
    3be9fdd557e6df449de93c2101973fb011699b3d

Change-Id: I98f0f5f760a39d2d7e0dd11d33663ddb75f0b6fc
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
2022-12-16 17:15:57 +01:00
Joanna Farley
7b77bd0d1f Merge "fix(xilinx): resolve integer handling issue" into integration 2022-12-16 16:59:44 +01:00
Sandrine Bailleux
bba0e7ebd6 Merge "fix(intel): missing NCORE CCU snoop filter fix in BL2" into integration 2022-12-16 15:37:07 +01:00
Akshay Belsare
4e46db40fc fix(xilinx): resolve integer handling issue
OEN Number 48 to 63 is for Trusted App and OS.
GET_SMC_OEN limits the return value of OEN number to 63 by bitwise AND
operation with 0x3F. Thus the upper limit check for OEN value returned
by GET_SMC_OEN is not required.
Removing the upper limit check for the OEN value returned by GET_SMC_OEN
resolves integer handling issue CONSTANT_EXPRESSION_RESULT

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: Ie04a4e2fb7cc85ec6055a5662736a805a89f7085
2022-12-16 17:43:43 +05:30