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fix(cpus): workaround for Cortex-A78 erratum 2772019

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Cortex-A78 erratum 2772019 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0362da463eca777aa7a385bcdeb39b8549799f02
This commit is contained in:
Bipin Ravi 2022-12-15 14:48:21 -06:00
parent 31747f057b
commit b10afcce5f
3 changed files with 45 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -317,6 +317,10 @@ For Cortex-A78, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
For Cortex-A78 AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to

32
lib/cpus/aarch64/cortex_a78.S
View file

@ -326,6 +326,31 @@ func check_errata_2395406
b cpu_rev_var_ls
endfunc check_errata_2395406
/* ----------------------------------------------------
* Errata Workaround for Cortex-A78 Errata 2772019
* This applies to revisions <= r1p2 and is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ----------------------------------------------------
*/
func errata_a78_2772019_wa
mov x17, x30
bl check_errata_2772019
cbz x0, 1f
/* dsb before isb of power down sequence */
dsb sy
1:
ret x17
endfunc errata_a78_2772019_wa
func check_errata_2772019
/* Applies to all revisions <= r1p2 */
mov x1, #0x12
b cpu_rev_var_ls
endfunc check_errata_2772019
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
@ -434,6 +459,12 @@ func cortex_a78_core_pwr_dwn
mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
msr CORTEX_A78_CPUPWRCTLR_EL1, x0
#if ERRATA_A78_2772019
mov x15, x30
bl cpu_get_rev_var
bl errata_a78_2772019_wa
mov x30, x15
#endif /* ERRATA_A78_2772019 */
isb
ret
endfunc cortex_a78_core_pwr_dwn
@ -461,6 +492,7 @@ func cortex_a78_errata_report
report_errata ERRATA_A78_2242635, cortex_a78, 2242635
report_errata ERRATA_A78_2376745, cortex_a78, 2376745
report_errata ERRATA_A78_2395406, cortex_a78, 2395406
report_errata ERRATA_A78_2772019, cortex_a78, 2772019
report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
ldp x8, x30, [sp], #16

9
lib/cpus/cpu-ops.mk
View file

@ -357,6 +357,11 @@ ERRATA_A78_2376745 ?=0
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
ERRATA_A78_2395406 ?=0
# Flag to apply erratum 2772019 workaround during powerdown. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still
# open.
ERRATA_A78_2772019 ?=0
# Flag to apply erratum 1941500 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_1941500 ?=0
@ -1011,6 +1016,10 @@ $(eval $(call add_define,ERRATA_A78_2376745))
$(eval $(call assert_boolean,ERRATA_A78_2395406))
$(eval $(call add_define,ERRATA_A78_2395406))
# Process ERRATA_A78_2772019 flag
$(eval $(call assert_boolean,ERRATA_A78_2772019))
$(eval $(call add_define,ERRATA_A78_2772019))
# Process ERRATA_A78_AE_1941500 flag
$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
$(eval $(call add_define,ERRATA_A78_AE_1941500))