Update the libfdt source files, the upstream commit is 73e0f143b73d
("libfdt: fdt_strerror(): Fix comparison warning").
This brings us the fixes for the signed/unsigned comparison warnings,
so platforms can enable -Wsign-compare now.
Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
With -Wsign-compare, compilers issue a warning in the SPMD code:
====================
services/std_svc/spmd/spmd_pm.c:35:22: error: comparison of integer
expressions of different signedness: 'int' and 'unsigned int'
[-Werror=sign-compare]
35 | if ((id < 0) || (id >= PLATFORM_CORE_COUNT)) {
| ^~
cc1: all warnings being treated as errors
====================
Since we just established that "id" is positive, we can safely cast it
to an unsigned type to make the comparison have matching types.
Change-Id: I6ef24804c88136d7e3f15de008e4fea854f10ffe
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.
This patch provides documentation support for Morello platform.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2
stm32mp15_optee_defconfig has been dropped from U-Boot as it became
identical to stm32mp15_trusted_defconfig.
Furthermore give a hint how OP-TEE is supposed to be installed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213
This patch makes changes required to get the morello
platform working with the tip of TF-A.
Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updated to reflect the
use of new version.
Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores
As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.
Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)
The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.
Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".
Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The application cores of the FPGAs used in Arm Ltd. start execution at
address 0x0. This is the location of some (emulated) ROM area (which can
be written to by the uploading tool).
Since the arm_fpga port is configured to run from DRAM, we load BL31 to
the beginning of DRAM (mapped at 2GB). This requires some small
trampoline code in the "ROM" to jump to the BL31 entry point.
To avoid some extra magic binary, add a tiny assembly file with that
trivial jump instruction to the tree, so this binary can be created
alongside BL31.
Change-Id: I9e4439fc0f093fa24dd49a8377c9edb030fbb477
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.
Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.
Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Statistical Profiling Extension (SPE) is an architectural feature we
can safely detect at runtime. However it still relies on one piece of
platform-specific information: the interrupt line it is connected
to. This requires SPE to be described in a devicetree node.
Since SPE support varies with the CPU cores found on an FPGA image, we
should detect the presence of SPE at runtime, and remove a potentially
existing SPE PMU node from the DT.
This allows to always have the SPE node in a generic devicetree file,
without risking exposing it on a CPU without this feature.
Change-Id: I73d83ea8509b03fe7bba20b9cce8d1335035fa31
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The size of a GICv3 redistributor region depends on the number of
cores in the system. For the ARM FPGA port, we detect the topology at
runtime, and adjust the CPU DT nodes accordingly.
Now the size of the GICR region must also be adjusted, or Linux will
fail to initialise the GICv3.
Use the newly introduced function to overwrite the GICR size entry in
the GICv3 reg property. We count the number of existing cores by
iterating over the GICR frames until we find the LAST bit set in TYPER.
Change-Id: Ib69565600859de9b1b15ceb8495172cd26d16fce
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
We now have code to detect the CPU topology at runtime, and can also
populate the CPU nodes in a devicetree accordingly. This is used by the
ARM FPGA port, for instance.
But also a GICv3 compatible interrupt controller provides MMIO frames
per core, so the size of this region needs to be adjusted in the DT,
to match the number of cores as well.
Provide a generic function to find the GICv3 interrupt controller in
the DT, then adjust the "reg" entry to match the number of detected
cores. Since the size of the GICR frame per cores differs between
GICv4 and GICv3, this size is supplied as a parameter to the function.
The caller should determine the applicable value by either hardcoding
it or by observing GICR_TYPER.VLPIS.
Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.
For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.
Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.
Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for Morello Rainier CPUs
This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to take
the role of primary bootloader.
Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
This patch adds CPU support for the Rainier CPU which is
derived from Neoverse N1 r4p0 CPU and implements the
Morello capability architecture.
Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.
This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.
This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build
option to 1 (enabled by default only on arm_fpga platform).
This feature can be very dangerous on a production image and
therefore it MUST be disabled for Release images.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.
However, the flash memory used for the mem_protect region was not
mapped. This results in a crash when an OS calls PSCI MEM_PROTECT.
To fix this map the flash region used for mem_protect.
Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
MCKPROT hardening in RCC mandates that both bits RCC[TZEN] and
RCC[MCKPROT] are enabled. This change fixes stm32mp1_rcc_is_mckprot()
to check both bits, not RCC[MCKPROT] only.
This change also updates stm32mp1_rcc_is_secure() for consistency.
Change-Id: If1f07babdcb5677906ddbf974d9dc17255d4e174
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Depending on compiler, the issue about bool or uint*_t not defined can
appear.
Correct this by adding stdbool.h and stdint.h includes in etzpc.h.
Change-Id: If1419dc511efbe682459fa4a776481fa52a38aa3
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The ICR static flags are cleared before sending a command.
The SDMMC_DCTRLR register is set to 0 if no data is expected on a given
command or on the next command in case of CMD55.
Change-Id: I5ae172a484218f53160e98b3684967c6960475a6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The retries number should be 3.
A warning message is added in mmc_block_read(), and the code is refactored.
Change-Id: I577c7dd91c451c7580b1660042cb5fe26ee3fa12
Signed-off-by: Yann Gautier <yann.gautier@st.com>
nand_wait_ready is called with a millisecond delay
but the timeout used a micro second. Fixing the conversion
in the timeout call.
The prototype of the function is also changed to use an unsigned int
parameter.
Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change the detection message from WARN to INFO when macronix
NOR is detected.
Change-Id: I488696f1fb75b823e85decfcd6cd32e7b36a6c2e
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The call to fdt_get_status(node) has to be done after the DT is found
to be valid.
Fixes: 1fc2130c5 stm32mp1: update device tree and gpio functions
Change-Id: I70f803aae3dde128a9e740f54c8837b64cb1a244
Signed-off-by: Yann Gautier <yann.gautier@st.com>
While restarting a new hash computation, STR register
is not cleared. It needs to be written before each
computation.
Change-Id: If65902dd21f9c139ec5da3ca87721232f73710db
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A
The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.
There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.
STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.
Some reordering is done in other files, and realign with kernel DT files.
The DDR files are generated with our internal tool, no changes in the
registers values.
Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
