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Merge "Workaround for Cortex A77 erratum 1508412" into integration
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commit
c36aa3cfa5
4 changed files with 88 additions and 0 deletions
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@ -251,6 +251,9 @@ For Cortex-A76, the following errata build flags are defined :
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For Cortex-A77, the following errata build flags are defined :
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- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
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CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
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- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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@ -24,4 +24,11 @@
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#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3
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#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4
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#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5
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#endif /* CORTEX_A77_H */
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@ -21,6 +21,70 @@
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#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1508412.
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* This applies only to revision <= r1p0 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1508412_wa
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/*
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* Compare x0 against revision r1p0
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*/
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mov x17, x30
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bl check_errata_1508412
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cbz x0, 3f
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/*
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* Compare x0 against revision r0p0
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*/
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bl check_errata_1508412_0
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cbz x0, 1f
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FFE00000
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msr CORTEX_A77_CPUPMR_EL3, x0
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ldr x0, =0x4004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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ldr x0, =0x1
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8C00040
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FFE00040
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msr CORTEX_A77_CPUPMR_EL3, x0
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b 2f
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1:
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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msr CORTEX_A77_CPUPOR_EL3, x0
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ldr x0, =0x00FF600000
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msr CORTEX_A77_CPUPMR_EL3, x0
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ldr x0, =0x00E8E00080
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msr CORTEX_A77_CPUPOR2_EL3, x0
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ldr x0, =0x00FFE000C0
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msr CORTEX_A77_CPUPMR2_EL3, x0
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2:
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ldr x0, =0x04004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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isb
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3:
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ret x17
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endfunc errata_a77_1508412_wa
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func check_errata_1508412
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1508412
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func check_errata_1508412_0
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mov x1, #0x0
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b cpu_rev_var_ls
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endfunc check_errata_1508412_0
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1800714.
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* This applies to revision <= r1p1 of Cortex A77.
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@ -60,6 +124,11 @@ func cortex_a77_reset_func
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A77_1508412
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mov x0, x18
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bl errata_a77_1508412_wa
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#endif
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#if ERRATA_A77_1800714
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mov x0, x18
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bl errata_a77_1800714_wa
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@ -98,6 +167,7 @@ func cortex_a77_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A77_1508412, cortex_a77, 1508412
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report_errata ERRATA_A77_1800714, cortex_a77, 1800714
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ldp x8, x30, [sp], #16
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@ -278,6 +278,10 @@ ERRATA_A76_1800710 ?=0
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# to all revisions of Cortex A76 cpu.
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ERRATA_A76_1165522 ?=0
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# Flag to apply erratum 1508412 workaround during reset. This erratum applies
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# only to revision <= r1p0 of the Cortex A77 cpu.
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ERRATA_A77_1508412 ?=0
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# Flag to apply erratum 1800714 workaround during reset. This erratum applies
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# only to revision <= r1p1 of the Cortex A77 cpu.
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ERRATA_A77_1800714 ?=0
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@ -551,6 +555,10 @@ $(eval $(call add_define,ERRATA_A76_1800710))
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$(eval $(call assert_boolean,ERRATA_A76_1165522))
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$(eval $(call add_define,ERRATA_A76_1165522))
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# Process ERRATA_A77_1508412 flag
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$(eval $(call assert_boolean,ERRATA_A77_1508412))
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$(eval $(call add_define,ERRATA_A77_1508412))
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# Process ERRATA_A77_1800714 flag
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$(eval $(call assert_boolean,ERRATA_A77_1800714))
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$(eval $(call add_define,ERRATA_A77_1800714))
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