The function `spmd_handle_spmc_message` was added into SPMD for
potential cases of SPMC sending a message (through SMC conduit)
to the SPMD. There is no longer a use case for this scenario.
Instead, if such a message is received by SPMD, return FFA_ERROR.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I74eda4cc0edf99c83a96d10981cf6d9e727207f8
The DRTM get and set error previously returned SMC_UNK when these
SMCs were issued. This has been corrected to return an appropriate
error code on failure, and success otherwise.
Also,align the error code values with the specification.
Change-Id: I8f11f94f1ab097245003dbde97365fa54e0097ba
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
You can only bind a limited number of events in each range. If you
attempt to bind more, it was crashing. This patch makes it return an
error code instead.
Change-Id: Ib19f0f0780959ded244d45349d9d6c8607255c15
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.
Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management
This patch performs necessary simd context management operations for
context switch from NWd to SWD and vice versa.
Change-Id: Ife01fffc4e2a7f3deb9b6273424161c225fdbbfb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This patch demonstrates the trivial changes to transparently switch
the fpregs_context_* helpers to simd_ctx_* helpers.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I14bda6bd0ead1f34a570b59be8dec3ac40891c20
This patch moves EXTRACT_PARTNUM from errata abi includes
to arch.h which is part of common includes
Change-Id: Id8bbaf21566f3145a75cfa0dafec6823ed2df3a9
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
* changes:
fix(rmmd): remove the assert check for RMM_BASE
fix(std_svc): continue boot if rmmd_setup fails
fix(rmmd): ignore SMC FID when RMM image is not present
fix(rmmd): fail gracefully if RME is not enabled
fix(rmmd): handle RMMD manifest loading failure
Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.
Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.
Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.
* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.
* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.
* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".
* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.
Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).
As updating of TL's signature, register value of x1/r1 should be:
In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).
Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.
This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.
2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.
This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).
Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: 5aa7aa1d3a [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705
This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in the DRAM by the previous bootloader. So, providing the
RMM base address at compile time is not feasible for such platforms.
The assert check is now replaced with a runtime check for the RMM image.
Change-Id: I568cdb6f76f41d0dcdc7a95feb75e252a7c5c930
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the scenarios where RMM image
is not present.
Change-Id: Ie4de15fb98ae7226eda410e15f1a650108dd8fb3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.
Change-Id: I3c19d886d32c56837a1a0d260d5204da8b2d12f1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the same image on boards that do not
support RME too.
Change-Id: I0cacdd7afd85ed3581e90ea81f0a51d076adb875
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runtime.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If61be6200e28fcea7a5ad697393e83679f488abc
By tracing instruction execution, it is observed:
Placing plat_my_core_pos at top of functions translate by the compiler
into calling those functions even if the result is not consumed when not
printed.
plat_my_core_pos is used to retrieve the core id for the currently
running core, but effectively call sites are only consuming it for
verbosity purposes. Move plat_my_core_pos calls into the print functions
that require it.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia3549453b5e4de7c575a8887a4d19e318658d03e
As observed by tracing instruction execution the SMC_RET18
macro in spmd_smc_switch_state calls cm_get_context, however the
compiler expands it to multiple individual non-inlined calls to
this same function. Store the result of cm_get_context into a local
variable and use it in the macro such that this function is only called
once.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib4fa63aced2f07c67c057f54fef3780c85e91df7
spmd_get_context_by_mpidr calls plat_core_pos_by_mpidr defined in
platform's fvp_topology. This involves a lot of intricated inner calls
including access to power controller (taking/releasing a bakery lock).
Remove dependency from this function, and use plat_my_core_pos instead.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8e91858922e339de51056dba8803db74c8fd7420
'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.
So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.
Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* changes:
build: improve diagnostics for unrecognized toolchain tools
build(rzg): separate BL2 and BL31 SREC generation
build(rcar): separate BL2 and BL31 SREC generation
build: separate preprocessing from DTB compilation
build: remove `MAKE_BUILD_STRINGS` function
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest
Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.
Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:
0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls
Amend Debugfs FID's to use this range and id.
Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.
Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview
Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add support for vendor-specific el3 service. SMCCC 1.5 introduces
support for vendor-specific EL3 monitor calls.
SMCCC Documentation reference:
https://developer.arm.com/docs/den0028/latest
Change-Id: Id8bc43842eecdb7a8a2ec7f31a631e88fe4fe0b4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:
-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability
The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.
- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.
Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Currently, the macros used to denote feature implementation
in hardware follow a random pattern with a few macros having
suffix as SUPPORTED and a few using the suffix IMPLEMENTED.
This patch aligns the macro names uniformly using the suffix
IMPLEMENTED across all the features and removes unused macros
pertaining to the Enable feat mechanism.
FEAT_SUPPORTED --> FEAT_IMPLEMENTED
FEAT_NOT_SUPPORTED --> FEAT_NOT_IMPLEMENTED
Change-Id: I61bb7d154b23f677b80756a4b6a81f74b10cd24f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This function causes the build message to be generated and compiled in
two different ways, with one way done inside `build_macros.mk` and the
other done inside `windows.mk`, mostly because it's done by generating
the C file on the command line.
We can instead replace this whole build message generation sequence with
a simple standard C compilation command and a normal C file.
Change-Id: I8bc136380c9585ddeec9a11154ee39ef70526f81
Signed-off-by: Chris Kay <chris.kay@arm.com>
When loading OPTEE via an SMC after we start Linux, we end up changing
the interrupt settings which is a violation of the Linux kernel's
policies. This change sets the interrupt handler before we proceed to
starting the kernel and ignores any incoming interrupts that occur
before OPTEE is loaded.
Signed-off-by: Jeffrey Kardatzke<jkardatzke@google.com>
Change-Id: I7da5334498e14f4a703e8cc3eeff386e3ecc0882
NS EL1 context save and restore is taken by SPMC upon entering and
exiting S-EL2
BREAKING CHANGE: Corresponding support is needed in Hafnium SPMC
Change-Id: I8524f1229b3e13c2df4e4b5be3f12436289c30c7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
An "Incorrect expression (SIZEOF_MISMATCH)" bug was raised by coverity
on the memset for clearing the manifest structure. This patch resolves
that issue.
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Change-Id: I40431b972fc434d2b33f597813f22126d5d4cb70
This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.
Boot manifest version is bumped to v0.3
Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Iedc4e640fb7a4450ce5ce966ae76936d1b7b742d
For platforms that do not support EL3 interrupts, such as ones with
GICV2 controller, do not register handler for Group0 interrupt.
Change-Id: I34536c0db9806c7b4c12dd398c0e5c12119c7457
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The current SPSR updation code as part of the SDEI interrupt handler
code is outdated. This patch replaces the legacy code with a call to
an up-to-date create_spsr()
Change-Id: I1f5fdd41dd14f4b09601310fe881fa3783d7f505
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Currently the EL2 part of the context structure (el2_sysregs_t), is
mostly feature dependent.
For instance, CTX_HCRX_EL2 is only needed when FEAT_HCX
(ENABLE_FEAT_HCX=1) is set, but the entry is unconditionally added
in the EL2 context structure and thereby consuming memory even in
build configurations where FEAT_HCX is disabled.
Henceforth, all such context entries should be coupled/tied with
their respective feature enables and be optimized away when unused.
This would reduce the context memory allocation for platforms, that
dont enable/support all the architectural features at once.
Further, converting the assembly context-offset entries into
a c structure relies on garbage collection of the linker
removing unreferenced structures from memory, as well as aiding
in readability and future maintenance.
Change-Id: I0cf49498ee3033cb6f3ee3810331121b26627783
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Cortex-X4 erratum 2701112 is cat B erratum that applies to
revision r0p0 and is fixed in r0p1. This erratum affects
system configurations that do not use an Arm interconnect IP.
The workaround for this erratum is not implemented in EL3.
The erratum can be enabled/disabled on a platform level.
The flag is used when the errata ABI feature is enabled and can
assist the Kernel in the process of mitigation of the erratum.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN2432808/latest
Change-Id: I8ede1ee75b0ea1658369a0646d8af91d44a8759b
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
* changes:
feat(drtm): update DRTM version to 1.0
feat(drtm): update references to DRTM beta0
feat(drtm): for TPM features fw hash algorithm should be 16-bits
feat(drtm): add ACPI table region size to the DLME header
feat(drtm): update return code if secondary PE is not off
feat(drtm): add additional return codes
Update all references to DRTM beta0 to be 1.0 instead.
Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Ieda70f26f3be42f4705e9b267706674c94f120f2
The DRTM 1.0 spec defines an additional field in the DLME
header for an optional region in the DLME to hold ACPI tables.
Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Idba7fa6bd0fb4ef2bdffc24f4588720e1661e58c
DRTM 1.0 specifies that if any secondary PEs are not off
during a dynamic launch the return code must be
SECONDARY_PE_NOT_OFF.
Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Idcb1f3c60daa63a5bc994bdeacca8aab7066f628
Add additional return codes defined in the DRTM 1.0 spec.
Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: I1620e098edf4f070ac759a26ce3c7272faf2d8b2
Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
