fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -799,6 +799,11 @@ For Cortex-X3, the following errata build flags are defined :
   CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU.
   It is fixed in r1p1.
 
+- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3
+  CPU and affects system configurations that do not use an ARM interconnect
+  IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
+  in r1p2.
+
 - ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
   r1p1. It is fixed in r1p2.
@@ -884,10 +889,6 @@ For Cortex-A715, the following errata build flags are defined :
    Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
    It is fixed in r1p1.
 
--  ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
-   CPU and affects system configurations that do not use an ARM interconnect
-   IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
-   in r1p2.
 
 DSU Errata Workarounds
 ----------------------

lib/cpus/cpu-ops.mk

@@ -802,6 +802,10 @@ CPU_FLAG_LIST += ERRATA_X3_2615812
 # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
 CPU_FLAG_LIST += ERRATA_X3_2641945
 
+# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
+# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2701951
+
 # Flag to apply erratum 2742421 workaround on reset. This erratum applies
 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2742421
@@ -915,10 +919,6 @@ CPU_FLAG_LIST += ERRATA_A715_2429384
 # only to revision r1p0. It is fixed in r1p1.
 CPU_FLAG_LIST += ERRATA_A715_2561034
 
-# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
-# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
-CPU_FLAG_LIST += ERRATA_A715_2701951
-
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 CPU_FLAG_LIST += ERRATA_DSU_798953

plat/arm/board/fvp/fvp_cpu_errata.mk

@@ -16,7 +16,7 @@ NEOVERSE_N2_H_INC	:= 1
 NEOVERSE_V1_H_INC	:= 1
 CORTEX_A78_AE_H_INC	:= 1
 CORTEX_A710_H_INC	:= 1
-CORTEX_A715_H_INC 	:= 1
+CORTEX_X3_H_INC		:= 1
 CORTEX_A78C_H_INC	:= 1
 CORTEX_X2_H_INC		:= 1
 $(eval $(call add_define, CORTEX_A78_H_INC))
@@ -24,7 +24,7 @@ $(eval $(call add_define, NEOVERSE_N2_H_INC))
 $(eval $(call add_define, NEOVERSE_V1_H_INC))
 $(eval $(call add_define, CORTEX_A78_AE_H_INC))
 $(eval $(call add_define, CORTEX_A710_H_INC))
-$(eval $(call add_define, CORTEX_A715_H_INC))
+$(eval $(call add_define, CORTEX_X3_H_INC))
 $(eval $(call add_define, CORTEX_A78C_H_INC))
 $(eval $(call add_define, CORTEX_X2_H_INC))
 endif

services/std_svc/errata_abi/cpu_errata_info.h

@@ -12,11 +12,11 @@
 
 #if __aarch64__
 #include <cortex_a710.h>
-#include <cortex_a715.h>
 #include <cortex_a78.h>
 #include <cortex_a78_ae.h>
 #include <cortex_a78c.h>
 #include <cortex_x2.h>
+#include <cortex_x3.h>
 #include <neoverse_n2.h>
 #include <neoverse_v1.h>
 #include <neoverse_v2.h>

services/std_svc/errata_abi/errata_abi_main.c

@@ -101,15 +101,15 @@ struct em_cpu_list cpu_list[] = {
 },
 #endif /* NEOVERSE_V2_H_INC */
 
-#if CORTEX_A715_H_INC
+#if CORTEX_X3_H_INC
 {
-	.cpu_partnumber = CORTEX_A715_MIDR,
+	.cpu_partnumber = CORTEX_X3_MIDR,
 	.cpu_errata_list = {
 		[0] = {2701951, 0x00, 0x11},
 		[1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
-#endif /* CORTEX_A715_H_INC */
+#endif /* CORTEX_X3_H_INC */
 
 };