There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.
Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.
Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>
This patch is used to enable platform enablement for
Agilex5 SoC FPGA.
New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3
This patch is used to implement system manager data
support for Agilex5 SoC FPGA.
1. Initial SM bring up
2. Support Candence SDMMC/NAND/COMBO PHY
3. Updated product name -> Agilex5
4. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82
This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8381b82eeed939b970a7410a6181a514f2c90caa
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b
This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I47f5c7f063fc443f29c2af612121abe672ed422b
This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Added power manager handoff implementation
3. Added sdram handoff implementation
4. Updated product name -> Agilex5
5. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I4b0176bc86c57823127bf41086306015d702577d
