Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:
Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575
Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.
Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
added the missing Neoverse N2 flag required for
enabling Neoverse N2 CPU in Errata ABI
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I06c6fa67e2f1ccc053f1b1b9261e189c56f4347a
Errata ABI feature specific build flag, flag to enable
CPUs in the cpu list, flags to test non-arm interconnect based
errata flags when enabled from a platform level.
Added to the FVP platform makefile to test the errata abi feature
implementation.
The flags to enable CPUs in the cpu list will be removed once
synchronized with the errata framework.
Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
