Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-17 18:14:24 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

Browse source 
* changes:
  feat(tc): move flash device to own node
  feat(tc): remove static memory used for fwu
  fix(tc): correct NS timer frame ID for TC
This commit is contained in:
Olivier Deprez 2024-10-14 14:39:08 +02:00 • committed by TrustedFirmware Code Review
commit e3b8e78d8d
3 changed files with 9 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
fdts/tc-base.dtsi
View file

@ -247,10 +247,6 @@
reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
}; };
fwu_mm {
reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>;
no-map;
};
}; };
memory { memory {

13
plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
View file

@ -99,11 +99,7 @@
memory@1 { memory@1 {
device_type = "ns-memory"; device_type = "ns-memory";
reg = reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
#ifdef TS_SP_FW_CONFIG
<0x0 0x08000000 0x0 0x4000000>,
#endif /* TS_SP_FW_CONFIG */
<0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
}; };
@ -117,4 +113,11 @@
device_type = "device-memory"; device_type = "device-memory";
reg = <0x0 PLAT_ARM_BOOT_UART_BASE 0x0 0x01000>; reg = <0x0 PLAT_ARM_BOOT_UART_BASE 0x0 0x01000>;
}; };
#ifdef TS_SP_FW_CONFIG
ns_flash {
device_type = "ns-device-memory";
reg = <0x0 V2M_FLASH0_BASE 0x0 V2M_FLASH0_SIZE>;
};
#endif
}; };

7
plat/arm/board/tc/include/platform_def.h
View file

@ -51,9 +51,6 @@
* | (4KB) | * | (4KB) |
* 0x8000_9000 ------------------ * 0x8000_9000 ------------------
* | ... | * | ... |
* 0xf8a0_0000 ------------------ TC_NS_FWU_BASE
* | FWU shmem |
* | (4MB) |
* 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE * 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE
* | OP-TEE shmem | * | OP-TEE shmem |
* | (2MB) | * | (2MB) |
@ -85,8 +82,6 @@
#define TC_NS_OPTEE_SIZE (2 * SZ_1M) #define TC_NS_OPTEE_SIZE (2 * SZ_1M)
#define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE) #define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE)
#define TC_NS_FWU_SIZE (4 * SZ_1M)
#define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE)
/* /*
* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
@ -228,7 +223,7 @@
V2M_FLASH0_SIZE, \ V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE) MT_DEVICE | MT_RO | MT_SECURE)
#define PLAT_ARM_NSTIMER_FRAME_ID 0 #define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0