mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
25a2fe3b74
With the updated firmware update implementation in the Trusted Services, it is no longer needed to carve out static memory. Memory will be allocated dynamically in U-Boot and shared with the firmware update secure partition of Trusted Services. Change-Id: I0fb128a458773236ee10526edfa1116b229e4d6e Signed-off-by: Davidson K <davidson.kumaresan@arm.com> Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
479 lines
15 KiB
C
479 lines
15 KiB
C
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <cortex_a520.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <plat/arm/board/common/board_css_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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/*
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* arm_def.h depends on the platform system counter macros, so must define the
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* platform macros before including arm_def.h.
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*/
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#if TARGET_PLATFORM == 4
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#ifdef ARM_SYS_CNTCTL_BASE
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#error "error: ARM_SYS_CNTCTL_BASE is defined prior to the PLAT_ARM_SYS_CNTCTL_BASE definition"
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#endif
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#define PLAT_ARM_SYS_CNTCTL_BASE UL(0x47000000)
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#define PLAT_ARM_SYS_CNTREAD_BASE UL(0x47010000)
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#endif
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/arm_spm_def.h>
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#include <plat/arm/css/common/css_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#include <plat/common/common_def.h>
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
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/*
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* The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
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* its base is ARM_AP_TZC_DRAM1_BASE.
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*
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* Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for:
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* - BL32_BASE when SPD_spmd is enabled
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* - Region to load secure partitions
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*
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*
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* 0x8000_0000 ------------------ TC_NS_DRAM1_BASE
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* | DTB |
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* | (32K) |
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* 0x8000_8000 ------------------
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* | NT_FW_CONFIG |
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* | (4KB) |
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* 0x8000_9000 ------------------
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* | ... |
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* 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE
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* | OP-TEE shmem |
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* | (2MB) |
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* 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE
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* | |
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* | SPMC |
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* | SP |
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* | (96MB) |
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* 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE
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* | AP |
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* | EL3 Monitor |
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* | SCP |
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* | (16MB) |
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* 0xFFFF_FFFF ------------------
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*
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*
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*/
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#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
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TC_TZC_DRAM1_SIZE)
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#define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */
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#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
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TC_TZC_DRAM1_SIZE - 1)
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#define TC_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE - \
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TC_TZC_DRAM1_SIZE)
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#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1)
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#define TC_NS_OPTEE_SIZE (2 * SZ_1M)
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#define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE)
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/*
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* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
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*/
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#define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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TC_NS_DRAM1_BASE, \
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TC_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
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TC_TZC_DRAM1_BASE, \
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TC_TZC_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE
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#define PLAT_ARM_HW_CONFIG_SIZE ULL(0x8000)
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#define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \
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PLAT_HW_CONFIG_DTB_BASE, \
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PLAT_ARM_HW_CONFIG_SIZE, \
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MT_MEMORY | MT_RO | MT_NS)
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/*
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* Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to
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* max size of BL32 image.
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*/
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#if defined(SPD_spmd)
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#define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000)
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#define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR
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#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
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#endif
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if defined(IMAGE_BL31)
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# if SPM_MM
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# define PLAT_ARM_MMAP_ENTRIES 9
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# define MAX_XLAT_TABLES 7
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# define PLAT_SP_IMAGE_MMAP_REGIONS 7
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
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# else
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 8
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# endif
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 5
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#elif !USE_ROMLIB
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 7
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#else
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# define PLAT_ARM_MMAP_ENTRIES 12
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# define MAX_XLAT_TABLES 6
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth. Current size is considering that TRUSTED_BOARD_BOOT
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* and MEASURED_BOOT is enabled.
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*/
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# define PLAT_ARM_MAX_BL2_SIZE 0x29000
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and
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* MEASURED_BOOT is enabled.
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*/
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#define PLAT_ARM_MAX_BL31_SIZE 0x60000
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# define PLATFORM_STACK_SIZE 0x1000
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#elif defined(IMAGE_BL2)
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# define PLATFORM_STACK_SIZE 0x1000
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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# if SPM_MM
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# define PLATFORM_STACK_SIZE 0x500
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# else
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# define PLATFORM_STACK_SIZE 0xa00
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# endif
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/*
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* In the current implementation the RoT Service request that requires the
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* biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
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* maximum required buffer size is calculated based on the platform-specific
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* needs of this request.
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*/
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#define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500
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#define TC_DEVICE_BASE 0x21000000
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#define TC_DEVICE_SIZE 0x5f000000
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#if defined(TARGET_FLAVOUR_FPGA)
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#undef V2M_FLASH0_BASE
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#undef V2M_FLASH0_SIZE
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#define V2M_FLASH0_BASE UL(0x0C000000)
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#define V2M_FLASH0_SIZE UL(0x02000000)
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#endif
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// TC_MAP_DEVICE covers different peripherals
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// available to the platform
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#define TC_MAP_DEVICE MAP_REGION_FLAT( \
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TC_DEVICE_BASE, \
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TC_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
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/* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */
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#define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE)
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#define PLAT_ARM_NSRAM_BASE 0x06000000
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#if TARGET_FLAVOUR_FVP
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#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
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#else /* TARGET_FLAVOUR_FPGA */
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#define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */
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#endif /* TARGET_FLAVOUR_FPGA */
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#if TARGET_PLATFORM <= 2
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#elif TARGET_PLATFORM >= 3
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#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
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#endif /* TARGET_PLATFORM >= 3 */
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#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
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#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
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#define TC_NS_MTE_SIZE (256 * SZ_1M)
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/* the SCP puts the carveout at the end of DRAM2 */
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#define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE)
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \
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INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \
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GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE)
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#define PLAT_ARM_SP_MAX_SIZE U(0x2000000)
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* Secure Watchdog Constants */
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#define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000)
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#define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000)
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#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
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#define SBSA_SECURE_WDOG_INTID 86
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#define PLAT_ARM_SCMI_CHANNEL_COUNT 1
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/* Index of SDS region used in the communication with SCP */
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#define SDS_SCP_AP_REGION_ID U(0)
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/* Index of SDS region used in the communication with RSE */
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#define SDS_RSE_AP_REGION_ID U(1)
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/*
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* Memory region for RSE's shared data storage (SDS)
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* It is placed right after the SCMI payload area.
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*/
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#define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \
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CSS_SCMI_PAYLOAD_SIZE_MAX)
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#define PLAT_ARM_CLUSTER_COUNT U(1)
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2
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#define PLAT_MAX_CPUS_PER_CLUSTER U(14)
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#else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
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#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
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#define PLAT_MAX_PE_PER_CPU U(1)
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#define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT)
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/* Message Handling Unit (MHU) base addresses */
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#if TARGET_PLATFORM <= 2
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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#elif TARGET_PLATFORM >= 3
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#define PLAT_CSS_MHU_BASE UL(0x46000000)
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#endif /* TARGET_PLATFORM >= 3 */
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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/* AP<->RSS MHUs */
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#if TARGET_PLATFORM <= 2
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#define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000)
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#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000)
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#elif TARGET_PLATFORM == 3
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#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
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#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000)
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#elif TARGET_PLATFORM == 4
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#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
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#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49010000)
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#endif
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* Physical and virtual address space limits for MMU in AARCH64
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x30080000)
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/*
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* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
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* SCP_BL2 size plus a little space for growth.
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*/
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#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000
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/*
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* PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
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* SCP_BL2U size plus a little space for growth.
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*/
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#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000
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#if TARGET_PLATFORM <= 2
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/* TZC Related Constants */
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#define PLAT_ARM_TZC_BASE UL(0x25000000)
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
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#define TZC400_OFFSET UL(0x1000000)
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#define TZC400_COUNT 4
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#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
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(n * TZC400_OFFSET))
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#define TZC_NSAID_DEFAULT U(0)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
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/*
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* The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to
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* ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as
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* secure. The second and third regions gives non secure access to rest of DRAM.
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*/
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#define TC_TZC_REGIONS_DEF \
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{TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
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TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
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#endif
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/* virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
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#if ARM_GPT_SUPPORT
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/*
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* This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h.
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* Offset of the FIP in the GPT image. BL1 component uses this option
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* as it does not load the partition table to get the FIP base
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* address. At sector 48 for TC to align with ATU page size boundaries (8KiB)
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* (i.e. after reserved sectors 0-47).
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* Offset = 48 * 512 = 0x6000
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*/
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#undef PLAT_ARM_FIP_OFFSET_IN_GPT
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#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000
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#endif /* ARM_GPT_SUPPORT */
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/* UART related constants */
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#define TC_UART0 0x2a400000
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#define TC_UART1 0x2a410000
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/*
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* TODO: if any more undefs are needed, it's better to consider dropping the
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* board_css_def.h include above
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*/
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#undef PLAT_ARM_BOOT_UART_BASE
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#undef PLAT_ARM_RUN_UART_BASE
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#undef PLAT_ARM_CRASH_UART_BASE
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#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
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#undef PLAT_ARM_RUN_UART_CLK_IN_HZ
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#if TARGET_FLAVOUR_FVP
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#define PLAT_ARM_BOOT_UART_BASE TC_UART1
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#define TC_UARTCLK 7372800
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#else /* TARGET_FLAVOUR_FPGA */
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#define PLAT_ARM_BOOT_UART_BASE TC_UART0
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#if TARGET_PLATFORM <= 2
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#define TC_UARTCLK 5000000
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#elif TARGET_PLATFORM >= 3
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#define TC_UARTCLK 3750000
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#endif /* TARGET_PLATFORM >= 3 */
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#undef ARM_CONSOLE_BAUDRATE
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#define ARM_CONSOLE_BAUDRATE 38400
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#endif /* TARGET_FLAVOUR_FPGA */
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#define PLAT_ARM_RUN_UART_BASE TC_UART0
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
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#if TARGET_PLATFORM == 3
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#define NCI_BASE_ADDR UL(0x4F000000)
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#ifdef TARGET_FLAVOUR_FPGA
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#define MCN_ADDRESS_SPACE_SIZE 0x00120000
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#else
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#define MCN_ADDRESS_SPACE_SIZE 0x00130000
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#endif /* TARGET_FLAVOUR_FPGA */
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#define MCN_OFFSET_IN_NCI 0x00C90000
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#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
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#define MCN_PMU_OFFSET 0x000C4000
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#define MCN_MICROARCH_OFFSET 0x000E4000
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#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
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#define MCN_SCR_OFFSET 0x4
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#define MCN_SCR_PMU_BIT 10
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#define MCN_INSTANCES 4
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#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
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(n * MCN_ADDRESS_SPACE_SIZE) + \
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MCN_PMU_OFFSET)
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#define MCN_MPAM_NS_OFFSET 0x000D0000
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#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET)
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#define MCN_MPAM_S_OFFSET 0x000D4000
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#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET)
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#define MPAM_SLCCFG_CTL_OFFSET 0x00003018
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#define SLC_RDALLOCMODE_SHIFT 8
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#define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT)
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#define SLC_WRALLOCMODE_SHIFT 12
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#define SLC_WRALLOCMODE_MASK (3 << SLC_WRALLOCMODE_SHIFT)
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|
|
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#define SLC_DONT_ALLOC 0
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|
#define SLC_ALWAYS_ALLOC 1
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#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
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|
|
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#define MCN_CONFIG_OFFSET 0x204
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#define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET)
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#define MCN_CONFIG_SLC_PRESENT_BIT 3
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|
|
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/*
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* TC3 CPUs have the same definitions for:
|
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* CORTEX_{A520|A725|X925}_CPUECTLR_EL1
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* CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT
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* Define the common macros for easier using.
|
|
*/
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#define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1
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|
#define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT
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#endif /* TARGET_PLATFORM == 3 */
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|
|
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#define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12)
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|
|
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#endif /* PLATFORM_DEF_H */
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