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Merge "fix(intel): handle cold reset via physical reset switch" into integration

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Mark Dykes 2025-01-13 20:13:04 +01:00 • committed by TrustedFirmware Code Review
commit d0658e6086
2 changed files with 7 additions and 2 deletions
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3
plat/intel/soc/agilex5/bl31_plat_setup.c
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@ -196,6 +196,9 @@ void bl31_plat_arch_setup(void)
NOTICE("BL31: CPU ID = %x\n", cpuid); NOTICE("BL31: CPU ID = %x\n", cpuid);
INFO("BL31: Invalidate Data cache\n"); INFO("BL31: Invalidate Data cache\n");
invalidate_dcache_all(); invalidate_dcache_all();
/* Invalidate for NS EL2 and EL1 */
invalidate_cache_low_el();
} }
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */ /* Get non-secure image entrypoint for BL33. Zephyr and Linux */

6
plat/intel/soc/agilex5/soc/agilex5_cache.S
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@ -15,14 +15,16 @@
* -------------------------------------------------------- * --------------------------------------------------------
*/ */
func invalidate_cache_low_el func invalidate_cache_low_el
mrs x0,SCR_EL3 mrs x0, SCR_EL3
orr x1,x0,#SCR_NS_BIT orr x1, x0, #SCR_NS_BIT
msr SCR_EL3, x1 msr SCR_EL3, x1
isb isb
tlbi ALLE2 tlbi ALLE2
dsb sy dsb sy
tlbi ALLE1 tlbi ALLE1
dsb sy dsb sy
msr SCR_EL3, x0
isb
endfunc invalidate_cache_low_el endfunc invalidate_cache_low_el
.pushsection .text.asm_dcache_level, "ax" .pushsection .text.asm_dcache_level, "ax"