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fix(intel): handle cold reset via physical reset switch

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On the Agilex5 platform when cold reset is issued via CLI application
in the OS, it is received in the BL31 via a SMC call and handled
accordingly like flush/invalidate the caches. However, when the cold
reset is issued via an external switch these handlings are missed.
This patch addresses those missed cache operations.

Also, this patch is to restoring SCR_EL3 NS bit to its previous value
in order to avoid unintended behavior especially if subsequent code
expects the SCR_EL3 register to be in its original configuration.

Change-Id: I9737f2db649e483ba61fffa6eeb0b56a9d15074a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-11-09 00:14:47 +08:00
parent 9ef62bd88d
commit bf3877e072
2 changed files with 7 additions and 2 deletions
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3
plat/intel/soc/agilex5/bl31_plat_setup.c
View file

@ -196,6 +196,9 @@ void bl31_plat_arch_setup(void)
NOTICE("BL31: CPU ID = %x\n", cpuid);
INFO("BL31: Invalidate Data cache\n");
invalidate_dcache_all();
/* Invalidate for NS EL2 and EL1 */
invalidate_cache_low_el();
}
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */

6
plat/intel/soc/agilex5/soc/agilex5_cache.S
View file

@ -15,14 +15,16 @@
* --------------------------------------------------------
*/
func invalidate_cache_low_el
mrs x0,SCR_EL3
orr x1,x0,#SCR_NS_BIT
mrs x0, SCR_EL3
orr x1, x0, #SCR_NS_BIT
msr SCR_EL3, x1
isb
tlbi ALLE2
dsb sy
tlbi ALLE1
dsb sy
msr SCR_EL3, x0
isb
endfunc invalidate_cache_low_el
.pushsection .text.asm_dcache_level, "ax"