diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index c090117a0..ab0392895 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -196,6 +196,9 @@ void bl31_plat_arch_setup(void)
 	NOTICE("BL31: CPU ID = %x\n", cpuid);
 	INFO("BL31: Invalidate Data cache\n");
 	invalidate_dcache_all();
+
+	/* Invalidate for NS EL2 and EL1 */
+	invalidate_cache_low_el();
 }
 
 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
diff --git a/plat/intel/soc/agilex5/soc/agilex5_cache.S b/plat/intel/soc/agilex5/soc/agilex5_cache.S
index 52ed5d358..f8c6a2df8 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_cache.S
+++ b/plat/intel/soc/agilex5/soc/agilex5_cache.S
@@ -15,14 +15,16 @@
 	 * --------------------------------------------------------
 	 */
 func invalidate_cache_low_el
-	mrs	x0,SCR_EL3
-	orr	x1,x0,#SCR_NS_BIT
+	mrs	x0, SCR_EL3
+	orr	x1, x0, #SCR_NS_BIT
 	msr	SCR_EL3, x1
 	isb
 	tlbi	ALLE2
 	dsb	sy
 	tlbi	ALLE1
 	dsb	sy
+	msr	SCR_EL3, x0
+	isb
 endfunc invalidate_cache_low_el
 
 .pushsection .text.asm_dcache_level, "ax"