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Merge changes I5aabe415,Ief6fb4fc into integration

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* changes:
  feat(stm32mp15-fdts): add SP_MIN versions of DT files
  feat(st): use dedicated version of DT for SP_MIN
This commit is contained in:
Madhukar Pappireddy 2025-02-27 16:21:14 +01:00 • committed by TrustedFirmware Code Review
commit c8054c8d58
12 changed files with 310 additions and 72 deletions
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7
fdts/stm32mp157a-dk1-sp_min-fw-config.dts Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
*/
#define DDR_SIZE 0x20000000 /* 512MB */
#include "stm32mp15-fw-config.dtsi"

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fdts/stm32mp157a-dk1-sp_min.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp157a-dk1.dts"
/ {
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board (SP_MIN)";
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
};

7
fdts/stm32mp157c-dk2-sp_min-fw-config.dts Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
*/
#define DDR_SIZE 0x20000000 /* 512MB */
#include "stm32mp15-fw-config.dtsi"

69
fdts/stm32mp157c-dk2-sp_min.dts Normal file
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@ -0,0 +1,69 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp157c-dk2.dts"
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board (SP_MIN)";
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
};

7
fdts/stm32mp157c-ed1-sp_min-fw-config.dts Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
*/
#define DDR_SIZE 0x40000000 /* 1GB */
#include "stm32mp15-fw-config.dtsi"

69
fdts/stm32mp157c-ed1-sp_min.dts Normal file
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@ -0,0 +1,69 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp157c-ed1.dts"
/ {
model = "STMicroelectronics STM32MP157C eval daughter (SP_MIN)";
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
};

34
fdts/stm32mp157c-ed1.dts
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* /*
* Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/ */
/dts-v1/; /dts-v1/;
@ -195,43 +195,13 @@
CLK_AXI_PLL2P CLK_AXI_PLL2P
CLK_MCU_PLL3P CLK_MCU_PLL3P
CLK_RTC_LSE CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE CLK_CKPER_HSE
CLK_FMC_ACLK CLK_FMC_ACLK
CLK_QSPI_ACLK CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>; >;
st,clkdiv = < st,clkdiv = <
@ -244,8 +214,6 @@
DIV(DIV_APB4, 1) DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2) DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23) DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>; >;
st,pll_vco { st,pll_vco {

7
fdts/stm32mp157c-ev1-sp_min-fw-config.dts Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (c) 2025, STMicroelectronics - All Rights Reserved
*/
#define DDR_SIZE 0x40000000 /* 1GB */
#include "stm32mp15-fw-config.dtsi"

64
fdts/stm32mp157c-ev1-sp_min.dts Normal file
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@ -0,0 +1,64 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
*/
/dts-v1/;
#include "stm32mp157c-ed1-sp_min.dts"
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother (SP_MIN)";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
aliases {
serial1 = &usart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&fmc {
pinctrl-names = "default";
pinctrl-0 = <&fmc_pins_a>;
status = "okay";
nand-controller@4,0 {
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_b>;
uart-has-rtscts;
status = "disabled";
};

36
fdts/stm32mp15xx-dkx.dtsi
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/* /*
* Copyright (c) 2019-2024, STMicroelectronics - All Rights Reserved * Copyright (c) 2019-2025, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/ */
@ -199,43 +199,11 @@
CLK_AXI_PLL2P CLK_AXI_PLL2P
CLK_MCU_PLL3P CLK_MCU_PLL3P
CLK_RTC_LSE CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>; >;
st,clkdiv = < st,clkdiv = <
@ -248,8 +216,6 @@
DIV(DIV_APB4, 1) DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2) DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23) DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>; >;
st,pll_vco { st,pll_vco {

4
plat/st/common/common_rules.mk
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@ -1,5 +1,5 @@
# #
# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved # Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -41,7 +41,7 @@ check_dtc_version:
# Create DTB file for BL2 # Create DTB file for BL2
${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | $$(@D)/ ${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | $$(@D)/
$(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@ $(q)echo '#include "$(patsubst %.dts,%$(SP_EXT).dts,$(patsubst fdts/%,%,$<))"' > $@
$(q)echo '#include "${BL2_DTSI}"' >> $@ $(q)echo '#include "${BL2_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl2.dtb: ${BUILD_PLAT}/fdts/%-bl2.dts ${BUILD_PLAT}/fdts/%-bl2.dtb: ${BUILD_PLAT}/fdts/%-bl2.dts

9
plat/st/stm32mp1/platform.mk
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@ -1,5 +1,5 @@
# #
# Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
@ -105,6 +105,11 @@ FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DT
ifeq ($(AARCH32_SP),sp_min) ifeq ($(AARCH32_SP),sp_min)
BL32_DTSI := stm32mp15-bl32.dtsi BL32_DTSI := stm32mp15-bl32.dtsi
FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME))) FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME)))
ifneq (,$(wildcard $(patsubst %.dtb,fdts/%-sp_min.dts,$(DTB_FILE_NAME))))
ifeq (,$(findstring -sp_min,$(DTB_FILE_NAME)))
SP_EXT := -sp_min
endif
endif
endif endif
endif endif
@ -258,7 +263,7 @@ BL2_SOURCES += plat/st/stm32mp1/plat_ddr.c
ifeq ($(AARCH32_SP),sp_min) ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32 # Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | $$(@D)/ ${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | $$(@D)/
$(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@ $(q)echo '#include "$(patsubst %.dts,%$(SP_EXT).dts,$(patsubst fdts/%,%,$<))"' > $@
$(q)echo '#include "${BL32_DTSI}"' >> $@ $(q)echo '#include "${BL32_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts | $$(@D)/ ${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts | $$(@D)/