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AMU: Implement context save/restore for aarch32

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Add amu_context_save() and amu_context_restore() functions for aarch32

Change-Id: I4df83d447adeaa9d9f203e16dc5a919ffc04d87a
Signed-off-by: Joel Hutton <joel.hutton@arm.com>
This commit is contained in:
Joel Hutton 2017-12-21 15:21:20 +00:00 • committed by Dimitris Papastamos
parent ce213b9622
commit c70da54631
5 changed files with 77 additions and 23 deletions
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2
include/lib/aarch32/arch.h
View file

@ -544,7 +544,7 @@
#define AMCNTENCLR0 p15, 0, c13, c2, 4 #define AMCNTENCLR0 p15, 0, c13, c2, 4
#define AMCNTENSET0 p15, 0, c13, c2, 5 #define AMCNTENSET0 p15, 0, c13, c2, 5
#define AMCNTENCLR1 p15, 0, c13, c3, 0 #define AMCNTENCLR1 p15, 0, c13, c3, 0
#define AMCNTENSET1 p15, 0, c13, c1, 1 #define AMCNTENSET1 p15, 0, c13, c3, 1
/* Activity Monitor Group 0 Event Counter Registers */ /* Activity Monitor Group 0 Event Counter Registers */
#define AMEVCNTR00 p15, 0, c0 #define AMEVCNTR00 p15, 0, c0

2
include/lib/extensions/amu.h
View file

@ -7,10 +7,10 @@
#ifndef __AMU_H__ #ifndef __AMU_H__
#define __AMU_H__ #define __AMU_H__
#include <sys/cdefs.h> /* for CASSERT() */
#include <cassert.h> #include <cassert.h>
#include <platform_def.h> #include <platform_def.h>
#include <stdint.h> #include <stdint.h>
#include <sys/cdefs.h> /* for CASSERT() */
/* All group 0 counters */ /* All group 0 counters */
#define AMU_GROUP0_COUNTERS_MASK 0xf #define AMU_GROUP0_COUNTERS_MASK 0xf

2
lib/cpus/aarch64/cortex_a75_pubsub.c
View file

@ -5,8 +5,8 @@
*/ */
#include <cortex_a75.h> #include <cortex_a75.h>
#include <pubsub_events.h>
#include <platform.h> #include <platform.h>
#include <pubsub_events.h>
struct amu_ctx { struct amu_ctx {
uint64_t cnts[CORTEX_A75_AMU_NR_COUNTERS]; uint64_t cnts[CORTEX_A75_AMU_NR_COUNTERS];

93
lib/extensions/amu/aarch32/amu.c
View file

@ -5,6 +5,7 @@
*/ */
#include <amu.h> #include <amu.h>
#include <amu_private.h>
#include <arch.h> #include <arch.h>
#include <arch_helpers.h> #include <arch_helpers.h>
#include <platform.h> #include <platform.h>
@ -14,21 +15,26 @@
struct amu_ctx { struct amu_ctx {
uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS]; uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
}; };
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT]; static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
void amu_enable(int el2_unused) int amu_supported(void)
{ {
uint64_t features; uint64_t features;
features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT; features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
if ((features & ID_PFR0_AMU_MASK) != 1) return (features & ID_PFR0_AMU_MASK) == 1;
}
void amu_enable(int el2_unused)
{
if (!amu_supported())
return; return;
if (el2_unused) { if (el2_unused) {
uint64_t v; uint64_t v;
/* /*
* Non-secure access from EL0 or EL1 to the Activity Monitor * Non-secure access from EL0 or EL1 to the Activity Monitor
* registers do not trap to EL2. * registers do not trap to EL2.
@ -40,15 +46,64 @@ void amu_enable(int el2_unused)
/* Enable group 0 counters */ /* Enable group 0 counters */
write_amcntenset0(AMU_GROUP0_COUNTERS_MASK); write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
/* Enable group 1 counters */
write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
}
/* Read the group 0 counter identified by the given `idx`. */
uint64_t amu_group0_cnt_read(int idx)
{
assert(amu_supported());
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
return amu_group0_cnt_read_internal(idx);
}
/* Write the group 0 counter identified by the given `idx` with `val`. */
void amu_group0_cnt_write(int idx, uint64_t val)
{
assert(amu_supported());
assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
amu_group0_cnt_write_internal(idx, val);
isb();
}
/* Read the group 1 counter identified by the given `idx`. */
uint64_t amu_group1_cnt_read(int idx)
{
assert(amu_supported());
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
return amu_group1_cnt_read_internal(idx);
}
/* Write the group 1 counter identified by the given `idx` with `val`. */
void amu_group1_cnt_write(int idx, uint64_t val)
{
assert(amu_supported());
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
amu_group1_cnt_write_internal(idx, val);
isb();
}
void amu_group1_set_evtype(int idx, unsigned int val)
{
assert(amu_supported());
assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
amu_group1_set_evtype_internal(idx, val);
isb();
} }
static void *amu_context_save(const void *arg) static void *amu_context_save(const void *arg)
{ {
struct amu_ctx *ctx; struct amu_ctx *ctx;
uint64_t features; int i;
features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT; if (!amu_supported())
if ((features & ID_PFR0_AMU_MASK) != 1)
return (void *)-1; return (void *)-1;
ctx = &amu_ctxs[plat_my_core_pos()]; ctx = &amu_ctxs[plat_my_core_pos()];
@ -61,12 +116,14 @@ static void *amu_context_save(const void *arg)
* counter values from the future via the memory mapped view. * counter values from the future via the memory mapped view.
*/ */
write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK); write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK);
write_amcntenclr1(AMU_GROUP1_COUNTERS_MASK);
isb(); isb();
ctx->group0_cnts[0] = read64_amevcntr00(); for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
ctx->group0_cnts[1] = read64_amevcntr01(); ctx->group0_cnts[i] = amu_group0_cnt_read(i);
ctx->group0_cnts[2] = read64_amevcntr02();
ctx->group0_cnts[3] = read64_amevcntr03(); for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
return 0; return 0;
} }
@ -75,6 +132,7 @@ static void *amu_context_restore(const void *arg)
{ {
struct amu_ctx *ctx; struct amu_ctx *ctx;
uint64_t features; uint64_t features;
int i;
features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT; features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
if ((features & ID_PFR0_AMU_MASK) != 1) if ((features & ID_PFR0_AMU_MASK) != 1)
@ -86,19 +144,16 @@ static void *amu_context_restore(const void *arg)
assert(read_amcntenset0() == 0); assert(read_amcntenset0() == 0);
/* Restore group 0 counters */ /* Restore group 0 counters */
if (AMU_GROUP0_COUNTERS_MASK & (1U << 0)) for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
write64_amevcntr00(ctx->group0_cnts[0]); amu_group0_cnt_write(i, ctx->group0_cnts[i]);
if (AMU_GROUP0_COUNTERS_MASK & (1U << 1)) for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
write64_amevcntr01(ctx->group0_cnts[1]); amu_group1_cnt_write(i, ctx->group1_cnts[i]);
if (AMU_GROUP0_COUNTERS_MASK & (1U << 2))
write64_amevcntr02(ctx->group0_cnts[2]);
if (AMU_GROUP0_COUNTERS_MASK & (1U << 3))
write64_amevcntr03(ctx->group0_cnts[3]);
isb();
/* Enable group 0 counters */ /* Enable group 0 counters */
write_amcntenset0(AMU_GROUP0_COUNTERS_MASK); write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
/* Enable group 1 counters */
write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
return 0; return 0;
} }

1
lib/extensions/amu/aarch64/amu.c
View file

@ -172,7 +172,6 @@ static void *amu_context_restore(const void *arg)
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++) for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
if (AMU_GROUP1_COUNTERS_MASK & (1U << i)) if (AMU_GROUP1_COUNTERS_MASK & (1U << i))
amu_group1_cnt_write(i, ctx->group1_cnts[i]); amu_group1_cnt_write(i, ctx->group1_cnts[i]);
isb();
/* Restore group 0/1 counter configuration */ /* Restore group 0/1 counter configuration */
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK); write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);