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c70da54631
Add amu_context_save() and amu_context_restore() functions for aarch32 Change-Id: I4df83d447adeaa9d9f203e16dc5a919ffc04d87a Signed-off-by: Joel Hutton <joel.hutton@arm.com>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cortex_a75.h>
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#include <platform.h>
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#include <pubsub_events.h>
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struct amu_ctx {
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uint64_t cnts[CORTEX_A75_AMU_NR_COUNTERS];
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uint16_t mask;
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};
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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static void *cortex_a75_context_save(const void *arg)
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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unsigned int midr;
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unsigned int midr_mask;
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int i;
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midr = read_midr();
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
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if ((midr & midr_mask) != (CORTEX_A75_MIDR & midr_mask))
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return 0;
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/* Save counter configuration */
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ctx->mask = cortex_a75_amu_read_cpuamcntenset_el0();
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/* Ensure counters are disabled */
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cortex_a75_amu_write_cpuamcntenclr_el0(ctx->mask);
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isb();
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/* Save counters */
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for (i = 0; i < CORTEX_A75_AMU_NR_COUNTERS; i++)
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ctx->cnts[i] = cortex_a75_amu_cnt_read(i);
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return 0;
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}
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static void *cortex_a75_context_restore(const void *arg)
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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unsigned int midr;
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unsigned int midr_mask;
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int i;
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midr = read_midr();
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
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if ((midr & midr_mask) != (CORTEX_A75_MIDR & midr_mask))
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return 0;
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ctx = &amu_ctxs[plat_my_core_pos()];
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/* Counters were disabled in `cortex_a75_context_save()` */
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assert(cortex_a75_amu_read_cpuamcntenset_el0() == 0);
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/* Restore counters */
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for (i = 0; i < CORTEX_A75_AMU_NR_COUNTERS; i++)
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cortex_a75_amu_cnt_write(i, ctx->cnts[i]);
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isb();
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/* Restore counter configuration */
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cortex_a75_amu_write_cpuamcntenset_el0(ctx->mask);
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return 0;
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}
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_a75_context_save);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, cortex_a75_context_restore);
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