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https://github.com/ARM-software/arm-trusted-firmware.git
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AMU: Add assembler helper functions for aarch32
Change-Id: Id6dfe885a63561b1d2649521bd020367b96ae1af Signed-off-by: Joel Hutton <joel.hutton@arm.com>
This commit is contained in:
Joel Hutton
Dimitris Papastamos
parent
e45820dc54
commit
ce213b9622
3 changed files with 303 additions and 1 deletions
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@ -23,7 +23,8 @@ BL32_SOURCES += lib/pmf/pmf_main.c
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endif
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ifeq (${ENABLE_AMU}, 1)
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BL32_SOURCES += lib/extensions/amu/aarch32/amu.c
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BL32_SOURCES += lib/extensions/amu/aarch32/amu.c\
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lib/extensions/amu/aarch32/amu_helpers.S
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endif
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ifeq (${WORKAROUND_CVE_2017_5715},1)
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@ -558,4 +558,40 @@
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#define AMEVTYPER02 p15, 0, c13, c6, 2
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#define AMEVTYPER03 p15, 0, c13, c6, 3
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/* Activity Monitor Group 1 Event Counter Registers */
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#define AMEVCNTR10 p15, 0, c4
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#define AMEVCNTR11 p15, 1, c4
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#define AMEVCNTR12 p15, 2, c4
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#define AMEVCNTR13 p15, 3, c4
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#define AMEVCNTR14 p15, 4, c4
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#define AMEVCNTR15 p15, 5, c4
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#define AMEVCNTR16 p15, 6, c4
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#define AMEVCNTR17 p15, 7, c4
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#define AMEVCNTR18 p15, 0, c5
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#define AMEVCNTR19 p15, 1, c5
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#define AMEVCNTR1A p15, 2, c5
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#define AMEVCNTR1B p15, 3, c5
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#define AMEVCNTR1C p15, 4, c5
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#define AMEVCNTR1D p15, 5, c5
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#define AMEVCNTR1E p15, 6, c5
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#define AMEVCNTR1F p15, 7, c5
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/* Activity Monitor Group 1 Event Type Registers */
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#define AMEVTYPER10 p15, 0, c13, c14, 0
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#define AMEVTYPER11 p15, 0, c13, c14, 1
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#define AMEVTYPER12 p15, 0, c13, c14, 2
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#define AMEVTYPER13 p15, 0, c13, c14, 3
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#define AMEVTYPER14 p15, 0, c13, c14, 4
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#define AMEVTYPER15 p15, 0, c13, c14, 5
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#define AMEVTYPER16 p15, 0, c13, c14, 6
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#define AMEVTYPER17 p15, 0, c13, c14, 7
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#define AMEVTYPER18 p15, 0, c13, c15, 0
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#define AMEVTYPER19 p15, 0, c13, c15, 1
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#define AMEVTYPER1A p15, 0, c13, c15, 2
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#define AMEVTYPER1B p15, 0, c13, c15, 3
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#define AMEVTYPER1C p15, 0, c13, c15, 4
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#define AMEVTYPER1D p15, 0, c13, c15, 5
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#define AMEVTYPER1E p15, 0, c13, c15, 6
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#define AMEVTYPER1F p15, 0, c13, c15, 7
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#endif /* __ARCH_H__ */
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265
lib/extensions/amu/aarch32/amu_helpers.S
Normal file
265
lib/extensions/amu/aarch32/amu_helpers.S
Normal file
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@ -0,0 +1,265 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <assert_macros.S>
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#include <asm_macros.S>
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.globl amu_group0_cnt_read_internal
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.globl amu_group0_cnt_write_internal
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.globl amu_group1_cnt_read_internal
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.globl amu_group1_cnt_write_internal
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.globl amu_group1_set_evtype_internal
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/*
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* uint64_t amu_group0_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `r0`.
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*/
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func amu_group0_cnt_read_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 3] */
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mov r1, r0
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lsr r1, r1, #2
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cmp r1, #0
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of ldcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r1, 1f
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lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
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add r1, r1, r0
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bx r1
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1:
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ldcopr16 r0, r1, AMEVCNTR00 /* index 0 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR01 /* index 1 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR02 /* index 2 */
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bx lr
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ldcopr16 r0, r1, AMEVCNTR03 /* index 3 */
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bx lr
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endfunc amu_group0_cnt_read_internal
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/*
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* void amu_group0_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func amu_group0_cnt_write_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 3] */
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mov r2, r0
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lsr r2, r2, #2
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cmp r2, #0
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of stcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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1:
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stcopr16 r0,r1, AMEVCNTR00 /* index 0 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR01 /* index 1 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR02 /* index 2 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR03 /* index 3 */
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bx lr
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endfunc amu_group0_cnt_write_internal
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/*
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* uint64_t amu_group1_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `r0`.
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*/
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func amu_group1_cnt_read_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of ldcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r1, 1f
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lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */
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add r1, r1, r0
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bx r1
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1:
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ldcopr16 r0,r1, AMEVCNTR10 /* index 0 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR11 /* index 1 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR12 /* index 2 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR13 /* index 3 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR14 /* index 4 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR15 /* index 5 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR16 /* index 6 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR17 /* index 7 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR18 /* index 8 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR19 /* index 9 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1A /* index 10 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1B /* index 11 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1C /* index 12 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1D /* index 13 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1E /* index 14 */
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bx lr
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ldcopr16 r0,r1, AMEVCNTR1F /* index 15 */
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bx lr
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endfunc amu_group1_cnt_read_internal
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/*
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* void amu_group1_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func amu_group1_cnt_write_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of ldcopr16/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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1:
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stcopr16 r0,r1, AMEVCNTR10 /* index 0 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR11 /* index 1 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR12 /* index 2 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR13 /* index 3 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR14 /* index 4 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR15 /* index 5 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR16 /* index 6 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR17 /* index 7 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR18 /* index 8 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR19 /* index 9 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1A /* index 10 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1B /* index 11 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1C /* index 12 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1D /* index 13 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1E /* index 14 */
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bx lr
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stcopr16 r0,r1, AMEVCNTR1F /* index 15 */
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bx lr
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endfunc amu_group1_cnt_write_internal
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/*
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* void amu_group1_set_evtype_internal(int idx, unsigned int val);
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*
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* Program the AMU event type register indexed by `idx`
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* with the value `val`.
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*/
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func amu_group1_set_evtype_internal
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#if ENABLE_ASSERTIONS
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/* `idx` should be between [0, 15] */
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mov r2, r0
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lsr r2, r2, #4
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cmp r2, #0
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ASM_ASSERT(eq)
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/* val should be between [0, 65535] */
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mov r2, r1
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lsr r2, r2, #16
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cmp r2, #0
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of stcopr/bx lr instruction pair
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* in the table below.
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*/
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adr r2, 1f
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lsl r0, r0, #3 /* each stcopr/bx lr sequence is 8 bytes */
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add r2, r2, r0
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bx r2
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1:
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stcopr r0, AMEVTYPER10 /* index 0 */
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bx lr
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stcopr r0, AMEVTYPER11 /* index 1 */
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bx lr
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stcopr r0, AMEVTYPER12 /* index 2 */
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bx lr
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stcopr r0, AMEVTYPER13 /* index 3 */
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bx lr
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stcopr r0, AMEVTYPER14 /* index 4 */
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bx lr
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stcopr r0, AMEVTYPER15 /* index 5 */
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bx lr
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stcopr r0, AMEVTYPER16 /* index 6 */
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bx lr
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stcopr r0, AMEVTYPER17 /* index 7 */
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bx lr
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stcopr r0, AMEVTYPER18 /* index 8 */
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bx lr
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stcopr r0, AMEVTYPER19 /* index 9 */
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bx lr
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stcopr r0, AMEVTYPER1A /* index 10 */
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bx lr
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stcopr r0, AMEVTYPER1B /* index 11 */
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bx lr
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stcopr r0, AMEVTYPER1C /* index 12 */
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bx lr
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stcopr r0, AMEVTYPER1D /* index 13 */
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bx lr
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stcopr r0, AMEVTYPER1E /* index 14 */
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bx lr
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stcopr r0, AMEVTYPER1F /* index 15 */
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bx lr
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endfunc amu_group1_set_evtype_internal
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