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fix(zynqmp): conditional reservation of memory in DTB
When the TF-A is placed in DDR memory range, the DDR memory range is getting explicitly reserved in the default device tree by TF-A. This creates an error condition in the use case where Device tree is not present or it is present at a different location. To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced. The TF-A will reserve the DDR memory only when a valid DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build. Now the user has options, either manually reserve the desired DDR address range for TF-A in device tree or let TF-A access and modify the device tree, to reserve the DDR address range, in runtime using the build parameter. Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81 Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This commit is contained in:
Akshay Belsare
Joanna Farley
parent
88844f6de2
commit
c52a142b7c
4 changed files with 42 additions and 10 deletions
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@ -31,6 +31,7 @@ To build TF-A for JTAG DCC console:
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ZynqMP platform specific build options
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--------------------------------------
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- ``XILINX_OF_BOARD_DTB_ADDR`` : Specifies the base address of Device tree.
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- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
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- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
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- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
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@ -47,13 +48,33 @@ ZynqMP Debug behavior
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With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range
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due to size constraints.
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For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location
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of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF.
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of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. By default the
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above memory range will NOT be reserved in device tree.
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If the user wants to move the bl31 to a different DDR location, user can provide
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the DDR address location in the build command as follows,
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To reserve the above memory range in device tree, the device tree base address
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must be provided during build as,
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
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ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> bl31
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XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
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The default DTB base address for ZynqMP platform is 0x100000. This default value
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is not set in the code and to use this default address, user still needs to
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provide it through the build command as above.
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If the user wants to move the bl31 to a different DDR location, user can provide
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the DDR address location using the build time parameters ZYNQMP_ATF_MEM_BASE and
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ZYNQMP_ATF_MEM_SIZE.
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The DDR address must be reserved in the DTB by the user, either by manually
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adding the reserved memory node, in the device tree, with the required address
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range OR let TF-A modify the device tree on the run.
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To let TF-A access and modify the device tree, the DTB address must be provided
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to the build command as follows,
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
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ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \
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XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
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FSBL->TF-A Parameter Passing
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@ -171,7 +171,7 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
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}
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#endif
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#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
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#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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static void prepare_dtb(void)
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{
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void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
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@ -217,7 +217,7 @@ static void prepare_dtb(void)
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void bl31_platform_setup(void)
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{
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#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
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#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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prepare_dtb();
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#endif
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@ -250,7 +250,7 @@ void bl31_plat_arch_setup(void)
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plat_arm_interconnect_enter_coherency();
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const mmap_region_t bl_regions[] = {
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#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
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#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
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MT_MEMORY | MT_RW | MT_NS),
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#endif
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@ -1,5 +1,7 @@
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/*
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* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -83,15 +85,18 @@
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define XILINX_OF_BOARD_DTB_ADDR U(0x100000)
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#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
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#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
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#define PLAT_OCM_BASE U(0xFFFC0000)
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#define PLAT_OCM_LIMIT U(0xFFFFFFFF)
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#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#ifndef MAX_MMAP_REGIONS
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#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
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#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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#define MAX_MMAP_REGIONS 8
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#else
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#define MAX_MMAP_REGIONS 7
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@ -99,7 +104,7 @@
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#endif
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#ifndef MAX_XLAT_TABLES
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#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
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#if !IS_TFA_IN_OCM(BL31_BASE)
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#define MAX_XLAT_TABLES 8
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#else
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#define MAX_XLAT_TABLES 5
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@ -1,6 +1,8 @@
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#
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# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
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# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -75,6 +77,10 @@ ifdef ZYNQMP_SECURE_EFUSES
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$(eval $(call add_define,ZYNQMP_SECURE_EFUSES))
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endif
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ifdef XILINX_OF_BOARD_DTB_ADDR
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$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
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endif
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64/ \
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-Iplat/xilinx/common/include/ \
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