From c52a142b7ceb397b4d66cc90f2bc717acc7263cd Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Mon, 27 Feb 2023 12:04:26 +0530 Subject: [PATCH] fix(zynqmp): conditional reservation of memory in DTB When the TF-A is placed in DDR memory range, the DDR memory range is getting explicitly reserved in the default device tree by TF-A. This creates an error condition in the use case where Device tree is not present or it is present at a different location. To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced. The TF-A will reserve the DDR memory only when a valid DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build. Now the user has options, either manually reserve the desired DDR address range for TF-A in device tree or let TF-A access and modify the device tree, to reserve the DDR address range, in runtime using the build parameter. Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81 Signed-off-by: Akshay Belsare --- docs/plat/xilinx-zynqmp.rst | 29 +++++++++++++++++++---- plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 6 ++--- plat/xilinx/zynqmp/include/platform_def.h | 11 ++++++--- plat/xilinx/zynqmp/platform.mk | 6 +++++ 4 files changed, 42 insertions(+), 10 deletions(-) diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst index b2871df7f..f98106237 100644 --- a/docs/plat/xilinx-zynqmp.rst +++ b/docs/plat/xilinx-zynqmp.rst @@ -31,6 +31,7 @@ To build TF-A for JTAG DCC console: ZynqMP platform specific build options -------------------------------------- +- ``XILINX_OF_BOARD_DTB_ADDR`` : Specifies the base address of Device tree. - ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. - ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. - ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. @@ -47,13 +48,33 @@ ZynqMP Debug behavior With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range due to size constraints. For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location -of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. +of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. By default the +above memory range will NOT be reserved in device tree. -If the user wants to move the bl31 to a different DDR location, user can provide -the DDR address location in the build command as follows, +To reserve the above memory range in device tree, the device tree base address +must be provided during build as, make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ - ZYNQMP_ATF_MEM_BASE= ZYNQMP_ATF_MEM_SIZE= bl31 + XILINX_OF_BOARD_DTB_ADDR= bl31 + +The default DTB base address for ZynqMP platform is 0x100000. This default value +is not set in the code and to use this default address, user still needs to +provide it through the build command as above. + +If the user wants to move the bl31 to a different DDR location, user can provide +the DDR address location using the build time parameters ZYNQMP_ATF_MEM_BASE and +ZYNQMP_ATF_MEM_SIZE. + +The DDR address must be reserved in the DTB by the user, either by manually +adding the reserved memory node, in the device tree, with the required address +range OR let TF-A modify the device tree on the run. + +To let TF-A access and modify the device tree, the DTB address must be provided +to the build command as follows, + +make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ + ZYNQMP_ATF_MEM_BASE= ZYNQMP_ATF_MEM_SIZE= \ + XILINX_OF_BOARD_DTB_ADDR= bl31 FSBL->TF-A Parameter Passing diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 1d963e82a..0ebd0885a 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -171,7 +171,7 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, } #endif -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) static void prepare_dtb(void) { void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; @@ -217,7 +217,7 @@ static void prepare_dtb(void) void bl31_platform_setup(void) { -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) prepare_dtb(); #endif @@ -250,7 +250,7 @@ void bl31_plat_arch_setup(void) plat_arm_interconnect_enter_coherency(); const mmap_region_t bl_regions[] = { -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, MT_MEMORY | MT_RW | MT_NS), #endif diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index b46eb636e..aebce304e 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,15 +85,18 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define XILINX_OF_BOARD_DTB_ADDR U(0x100000) #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) #define PLAT_DDR_LOWMEM_MAX U(0x80000000) +#define PLAT_OCM_BASE U(0xFFFC0000) +#define PLAT_OCM_LIMIT U(0xFFFFFFFF) + +#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #ifndef MAX_MMAP_REGIONS -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) #define MAX_MMAP_REGIONS 8 #else #define MAX_MMAP_REGIONS 7 @@ -99,7 +104,7 @@ #endif #ifndef MAX_XLAT_TABLES -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if !IS_TFA_IN_OCM(BL31_BASE) #define MAX_XLAT_TABLES 8 #else #define MAX_XLAT_TABLES 5 diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 38e740802..4671f5f11 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -1,6 +1,8 @@ # # Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. # Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. +# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. +# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -75,6 +77,10 @@ ifdef ZYNQMP_SECURE_EFUSES $(eval $(call add_define,ZYNQMP_SECURE_EFUSES)) endif +ifdef XILINX_OF_BOARD_DTB_ADDR +$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) +endif + PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ -Iinclude/plat/arm/common/aarch64/ \ -Iplat/xilinx/common/include/ \