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Merge changes from topic "ip_smmu" into integration

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* changes:
  feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
  feat(tc): bind SMMU-700 with DPU on TC3
  refactor(tc): append binding for SMMU-700
This commit is contained in:
Manish V Badarkhe 2024-06-18 11:34:23 +02:00 • committed by TrustedFirmware Code Review
commit b6b44e1fce
4 changed files with 65 additions and 11 deletions
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33
fdts/tc-base.dtsi
View file

@ -482,9 +482,6 @@
scmi-perf-domain = <3>;
#endif /* TC_SCMI_PD_CTRL_EN */
#if TC_IOMMU_EN
iommus = <&smmu_700 0x200>;
#endif /* TC_IOMMU_EN */
pbha {
int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>,
<8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>,
@ -507,7 +504,18 @@
thermal-zone = "";
};
#if TC_IOMMU_EN
smmu_600: smmu@2ce00000 {
compatible = "arm,smmu-v3";
reg = <0 0x2ce00000 0 0x20000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
#iommu-cells = <1>;
status = "disabled";
};
smmu_700: iommu@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
@ -517,8 +525,20 @@
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
status = "disabled";
};
smmu_700_dpu: iommu@4002a00000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>;
interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 482 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 483 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
status = "disabled";
};
#endif /* TC_IOMMU_EN */
dp0: display@DPU_ADDR {
#address-cells = <1>;
@ -528,9 +548,6 @@
interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DPU";
DPU_CLK_ATTR1;
#if TC_IOMMU_EN
iommus = <&smmu_700 0x100>;
#endif /* TC_IOMMU_EN */
pl0: pipeline@0 {
reg = <0>;

9
fdts/tc2.dts
View file

@ -237,9 +237,18 @@
};
};
smmu_700: iommu@3f000000 {
status = "okay";
};
dp0: display@DPU_ADDR {
#if TC_SCMI_PD_CTRL_EN
power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
#endif
iommus = <&smmu_700 0x100>;
};
gpu: gpu@2d000000 {
iommus = <&smmu_700 0x200>;
};
};

31
fdts/tc3.dts
View file

@ -105,4 +105,35 @@
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";
};
smmu_700_dpu: iommu@4002a00000 {
status = "okay";
};
#else
smmu_600: smmu@2ce00000 {
status = "okay";
};
#endif
dp0: display@DPU_ADDR {
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
#else /* TARGET_FLAVOUR_FPGA */
iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
<&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
<&smmu_600 8>, <&smmu_600 9>;
#endif
};
gpu: gpu@2d000000 {
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700 0x200>;
#endif
};
};

3
plat/arm/board/tc/platform.mk
View file

@ -10,8 +10,6 @@ TARGET_FLAVOUR := fvp
TC_DPU_USE_SCMI_CLK := 1
# SCMI power domain control enable
TC_SCMI_PD_CTRL_EN := 1
# IOMMU: Enable the use of system or individual MMUs
TC_IOMMU_EN := 1
# System setup
CSS_USE_SCMI_SDS_DRIVER := 1
@ -76,7 +74,6 @@ $(eval $(call add_defines, \
TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
TC_IOMMU_EN \
))
CSS_LOAD_SCP_IMAGES := 1