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feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
The SMMU 600 is used on TC3 FPGA board with the display device, add the device tree binding for it. Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98ae945 Signed-off-by: Ben Horgan <ben.horgan@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
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2 changed files with 20 additions and 0 deletions
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@ -504,6 +504,18 @@
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thermal-zone = "";
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};
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smmu_600: smmu@2ce00000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x2ce00000 0 0x20000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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#iommu-cells = <1>;
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status = "disabled";
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};
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smmu_700: iommu@3f000000 {
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#iommu-cells = <1>;
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compatible = "arm,smmu-v3";
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@ -94,12 +94,20 @@
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smmu_700_dpu: iommu@4002a00000 {
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status = "okay";
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};
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#else
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smmu_600: smmu@2ce00000 {
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status = "okay";
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};
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#endif
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dp0: display@DPU_ADDR {
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
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#else /* TARGET_FLAVOUR_FPGA */
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iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
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<&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
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<&smmu_600 8>, <&smmu_600 9>;
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#endif
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};
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